7630 datasheet(116/238 Pages) RENESAS

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7630 Group User’s Manual

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2.4 Controller Area Network (CAN) module

2.4.5 Module initialization

Initializing the module comprises several steps. Before attempting to access the registers involved the following

items must be considered:

• Acceptance filter

The CAN acceptance code registers CACi (Figures 2.4.6 to 2.4.10) and CAN acceptance mask registers CAMi

(Figures 2.4.11 to 2.4.15) need to be initialized. For details on the acceptance filter see section 2.4.7.

• Bit timing

The time for the transmission of a single bit consists of four segments:

• Synchronization segment (SS)

• Propagation time segment (PTS)

• Phase buffer segment 1 (PBS1)

• Phase buffer segment 2 (PBS2)

SS is of fixed length (one time-quantum), but the length of PTS, PBS1/2 must be programmed by the bus timing

control registers CBTCONi (Figures 2.4.4 and 2.4.5). Figure 2.4.27 shows the segmentation of one bit-time and

the possible range for each segment to be programmed.

Note: The CAN specification defines the sum of all time quanta within one bit-time between 8 and 25.

Fig. 2.4.27 Segmentation of bit-time

The sample point is the point within a bit-time where the bus level is known as the value of that respective bit. Its

position is between phase buffer segment 1 and phase buffer segment 2. The sample point must be defined in

common for all active nodes on the network.

• Resynchronization jump width

The resynchronization jump width can be programmed via CBTCON2 (Figure 2.4.5).

Note: The CAN specification defines resynchronization jump width as min(4,Tpbs1).

• Sampling

The sampling control bit CBTCON1.4 (Figure 2.4.4) allows to decide the bit level based on either a single or

three samples. With single sampling, the level is sampled at the defined sample point (refer to Figure 2.4.27). Tri-

ple sampling takes two additional samples two and four cycles of f(XIN) before the defined sample point; the bit

level is decided on the majority of the three samples. Triple sampling implements a means of digital filtering

being appropriate if the bus signal is contaminated by noise.

• Baud rate

The module contains a programmable prescaler which is clocked by the MCUs internal clock frequency f

φ. This

prescaler allows division ratios of 1 to 1/16 (refer to Figure 2.4.4). The baud rate can be calculated as follows,

where p is the prescaler division ratio:

• Dominant polarity

The polarity control register PCON (Figure 2.2.9) allows to select the dominant level either “high” or “low”. This

setting depends on the transceiver; please refer to the specification of the device/circuit in use.

Segment

Range in time quanta

Min.

Max.

Tss

1 (fixed)

Tpts

Tpbs1

Tpbs2

PTS

PBS2

sample point

bit-time: tbt

Tss

Tpts

Tpbs1

Tpbs2

PBS1

CAN

------

fφ

p ts

p bs1

p bs2

(

)

⋅

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