HC210 datasheet(178/228 Pages) ALTERA

178 / 228 page

7–14

Altera Corporation

September 2008

HardCopy Series Handbook, Volume 1

The Compilation Report for both the Stratix II and HardCopy II

revisions of your project includes a Timing Constraints Check section

(Figure 7–6). This section reports all unconstrained paths based on the

coverage provided by the timing constraints used in the design. You

should examine this report and verify that all internal and I/O paths and

all clock domains are constrained for both setup and hold checks.

Figure 7–6. Classic Timing Analyzer Constraints Check in Compilation Report

When using Classic Timing Analyzer, just as when using the TimeQuest

timing analyzer, you should review the Quartus II timing report sections

in the Compilation Report and resolve all reported timing violations.

Constraining

Timing of

HardCopy Series

Devices

To ensure that the timing of the HardCopy device meets performance

goals, the HardCopy Design Center runs static timing analysis on the

design database. For this timing analysis to be meaningful, all timing

constraints and timing exceptions that you applied to the design for the

FPGA implementation, must also be used for the HardCopy

implementation. If you did not use timing constraints or you used only

partial timing constraints for the design, you must add constraints to

HC210 Datasheet(PDF) 178 Page - Altera Corporation