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HC210 Datasheet(PDF) 182 Page - Altera Corporation

Part # HC210
Description  HardCopy II Device Family
PDF  228 Pages
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Manufacturer  ALTERA [Altera Corporation]
Direct Link  http://www.altera.com
Logo ALTERA - Altera Corporation

HC210 Datasheet(HTML) 182 Page - Altera Corporation

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7–18
Altera Corporation
September 2008
HardCopy Series Handbook, Volume 1
Figure 7–9. Internal Input Delay Specification (Setup)
Figure 7–10 shows a generic circuit with an on-chip hold-time constraint.
Figure 7–10. Internal Input Delay Specification (Hold)
Primary Output Port Timing
You must specify the output port timing constraint for every primary
output port in the design and for the output path of every bidirectional
port. There are two ways to capture the output port timing, as described
in the following two sections.
tsu for a Primary Input Port
data
clk
tsu
Data
Path
Delay
Clock
Delay
tH for a Primary Input
data
clk
tH
Data
Path
Delay
Clock
Delay



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