HC210 datasheet(184/228 Pages) ALTERA

184 / 228 page

7–20

Altera Corporation

September 2008

HardCopy Series Handbook, Volume 1

Combinational Timing

In combinational timing circuits, a path exists from a primary input port

to a primary output port. This type of circuit does not contain any

registers. Therefore, it does not require a clock for constraint

specification. You only need the maximum and minimum delay from the

primary input port to the primary output port to constrain the path for

timing requirements. Figure 7–13 shows the placement requirement for a

combinational delay arc constraint in a generic circuit.

Figure 7–13. Combinational Timing Constraint

Timing Exceptions

Some circuit structures warrant special consideration. For example, you

can ignore all timing paths between two clock domains when a design

has more than one clock domain and the clock domains are not related.

You can ignore all timing paths using the static timing analysis tool by

specifying false paths for all signals that go from one clock domain to the

other clock domain(s). Additionally, some circuits are not intended to

operate in a single-clock cycle. These circuits require that you specify

multi-cycle clock exceptions.

After capturing the information, the Altera HCDC directly checks all

timing of the HardCopy series device before tape-out occurs. If any

timing violations occur in the HardCopy series device due to overly

aggressive timing constraints, Altera must fix them, or you must waive

them.

input

Data Path

Delay

Combinational Delay Arc

output

HC210 Datasheet(PDF) 184 Page - Altera Corporation