HC210 datasheet(183/228 Pages) ALTERA

183 / 228 page

Altera Corporation

7–19

September 2008

Constraining Timing of HardCopy Series Devices

External Output Delay Specification

One way to capture output port timing is to describe the external timing

environment, which is the maximum and minimum delay times of

external signals that are driven by the primary output ports of the

HardCopy series device. Figure 7–11 shows the external timing

constraint driven by the primary output port. The static timing analysis

tool uses this information to check that the on-chip timing of the output

signals is within the desired specification.

Figure 7–11. External Timing Constraint for a Primary Output Port

Internal Output Delay (Tco) Specification

This approach describes the acceptable maximum and minimum on-chip

clock-to-output (TCO) delay. For example, you can use this approach to

describe the time it takes from the active edge of the clock to the data

arriving at the primary output port. Figure 7–12 shows a generic circuit

with an on-chip TCO time constraint. In addition, there can be a minimum

TCO requirement.

Figure 7–12. On-Chip Clock-to-Output (Tco) Time Constraint

dff

Primary Output from

FPGA/HardCopy

Series Device

External Device

External Output Delay

Data Path

Delay

Data Path

Delay

HardCopy Device or FPGA

tco for a Primary Output Port

clk

Data

Path

Delay

Clock

Delay

tco

output

HC210 Datasheet(PDF) 183 Page - Altera Corporation