HC210 datasheet(179/228 Pages) ALTERA

179 / 228 page

Altera Corporation

7–15

September 2008

Constraining Timing of HardCopy Series Devices

make the design fully constrained, and use the same constraints for both

FPGA and HardCopy revisions in the flow. If you do not do this, you

cannot determine whether the HardCopy series device meets the

required timing of the end target system. The SDC format timing

constraints can be generated using the Quartus II SDC File Editor which

provides line numbering, syntax coloring, and call tips. You can enter

timing constraints and exceptions directly or specify them from the

Constraints menu. An example of the SDC commands is shown in the

following section.

The following constraints must be included:

■

Clock definitions

■

Primary input port timing

■

Primary output port timing

■

Combinational timing

■

Timing exceptions

For information on the SDC editor, refer to the TimeQuest Timing Analyzer

chapter in volume 3 of the Quartus II Handbook.

For more information on timing constraints for the TimeQuest timing

analyzer, refer to the TimeQuest Timing Analyzer chapter in volume 3 of

the Quartus II Handbook.

For more information on timing assignments for Classic Timing

Analyzer, refer to the Classic Timing Analyzer chapter in volume 3 of the

Quartus II Handbook.

Clock Definitions

You can use these definitions to describe the parameters of all different

clock domains in a design. Clock parameters that must be defined are

frequency, time at which the clock edge rises, time at which the clock edge

falls, clock uncertainty (for example: jitter, noise, and designed in timing

margin), and clock name. Figure 7–7 illustrates the attributes.

HC210 Datasheet(PDF) 179 Page - Altera Corporation