XRT72L13 datasheet(19/370 Pages) EXAR

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XRT72L13

M13 MULTIPLEXER/CLEAR CHANNEL DS3 FRAMER IC

PRELIMINARY

REV. P1.0.6

RxDS1Clk_10

Receive DS1/E1 Clock Output - Channel 10:

This pin outputs either a DS1 (1.544MHz) or an E1 (2.048MHz) clock

signal to the Terminal Equipment. The XRT72L13 will update the data

on the "RxDS1Data_10" line, upon the rising edge of this signal.

RxDS1Data_9

Receive DS1/E1 Data Output - Channel 9:

This pin outputs either a DS1 or E1 signal from the M12 multiplexer.

Each bit, within the DS1 or E1 data stream is output upon the rising

edge of RxDS1Clk_9.

RxDS1Clk_9

Receive DS1/E1 Clock Output - Channel 9:

This pin outputs either a DS1 (1.544MHz) or an E1 (2.048MHz) clock

signal to the Terminal Equipment. The XRT72L13 will update the data

on the "RxDS1Data_9" line, upon the rising edge of this signal.

RxDS1Data_8

Receive DS1/E1 Data Output - Channel 8:

This pin outputs either a DS1 or E1 signal from the M12 multiplexer.

Each bit, within the DS1 or E1 data stream is output upon the rising

edge of RxDS1Clk_8.

RxDS1Clk_8

Receive DS1/E1 Clock Output - Channel 8:

This pin outputs either a DS1 (1.544MHz) or an E1 (2.048MHz) clock

signal to the Terminal Equipment. The XRT72L13 will update the data

on the "RxDS1Data_8" line, upon the rising edge of this signal.

RxDS1Data_7

RxHDLC_Data_7

Receive DS1 Data Output - Channel 7/Receive HDLC Controller

Block Output - Bit 7:

The funtion of this output pin depends upon whether the XRT72L13 is

operating in the "Multiplexer/De-Multiplexer" Mode or in the "High

Speed HDLC Controller" Mode.

Receive DS1 Data Output - Channel 7: (Multiplexer/De-Multi-

plexer Mode):

This pin outputs a DS1 signal from the M12 multiplexer. Each bit,

within the DS1 data stream is output upon the rising edge of

RxDS1Clk_7.

NOTES:

1. This output pin is inactive if the corresponding M12 DEMUX is

de-multiplexing an ITU-T G.747 data stream.

2. This pin will output the contents of DS2 channel # 2, if M12

MUX # 2 is bypassed.

Receive HDLC Controller Block Output - Bit 7 (High Speed HDLC

Controller Mode)

This output pin along with RxHDLC_Data[0:6] output the contents of

all HDLC frames that have been received (via the DS3 payload) from

the remote terminal equipment.

The data on this output pin is updated upon the rising edge of "RxH-

DLCClk".

NOTE: This pin is inactive while the Receive HDLC Controller is

receiving the "Flag Sequence" octet.

PIN DESCRIPTIONS

PIN #NAME

TYPE

DESCRIPTION

XRT72L13 Datasheet(PDF) 19 Page - Exar Corporation

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