XRT72L13 datasheet(24/370 Pages) EXAR

24 / 370 page

XRT72L13

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M13 MULTIPLEXER/CLEAR CHANNEL DS3 FRAMER IC

REV. P1.0.6

PRELIMINARY

RxDS1Clk_1/

RxHDLCClk

Receive DS1/E1 Clock Output - Channel 0/Receive HDLC Con-

troller Clock Output:

The funtion of this output pin depends upon whether the XRT72L13 is

operating in the "Multiplexer/De-Multiplexer" Mode or in the "High

Speed HDLC Controller" Mode.

Receive DS1/E1 Clock Output - Channel 1 (Multiplexer/De-Multi-

plexer Mode):

This pin outputs either a DS1 (1.544MHz) or an E1 (2.048MHz) clock

signal to the Terminal Equipment. The XRT72L13 will update the data

on the "RxDS1Data_0" line, upon the rising edge of this signal.

Receive HDLC Clock Output pin (High Speed HDLC Controller

Mode)

The contents of the "received" HDLC frames are output via the

RxHDLC_Data[7:0] bus, upon the rising edge of this input pin.

RxDS1Data_0/

RxHDLC_Data_0

Receive DS1/E1 Data Output - Channel 0/Receive HDLC Control-

ler Block Output - Bit 0:

The funtion of this output pin depends upon whether the XRT72L13 is

operating in the "Multiplexer/De-Multiplexer" Mode or in the "High

Speed HDLC Controller" Mode.

Receive DS1/E1 Data Output - Channel 0 (Multiplexer/De-Multi-

plexer Mode)

This pin outputs either a DS1 or E1 signal from the M12 multiplexer.

Each bit, within the DS1 or E1 data stream is output upon the rising

edge of RxDS1Clk_0.

Receive HDLC Controller Block Output - Bit 0: (High Speed HDLC

Controller Mode)

This output pin along with RxHDLC_Data[1:7] output the contents of

all HDLC frames that have been received (via the DS3 payload) from

the remote terminal equipment.

The data on this output pin is updated upon the rising edge of "RxH-

DLCClk".

NOTE: This pin is inactive while the Receive HDLC Controller is

receiving the "Flag Sequence" octet.

VDD

****

Power Supply Pin

RxDS1Clk_0/

TxHDLCClk

Receive DS1/E1 Clock Output - Channel 0/Transmit HDLC Con-

troller Clock Output:

The funtion of this output pin depends upon whether the XRT72L13 is

operating in the "Multiplexer/De-Multiplexer" Mode or in the "High

Speed HDLC Controller" Mode.

Receive DS1/E1 Clock Output - Channel 0 (Multiplexer/De-Multi-

plexer Mode):

This pin outputs either a DS1 (1.544MHz) or an E1 (2.048MHz) clock

signal to the Terminal Equipment. The XRT72L13 will update the data

on the "RxDS1Data_0" line, upon the rising edge of this signal.

Transmit HDLC Controller Clock Output (High Speed HDLC Con-

troller Mode):

The data on the "TxHDLC_Data[7:0] bus, are latched into the "Trans-

mit HDLC Controller" block upon the rising edge of this clock signal.

RESET

Reset Input:

When this "active-low" signal is asserted, the Framer will be asyn-

chronously reset. Additionally, all outputs will be "tri-stated", and all

on-chip registers will be reset to their default values.

PIN DESCRIPTIONS

PIN #NAME

TYPE

DESCRIPTION

XRT72L13 Datasheet(PDF) 24 Page - Exar Corporation

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