XRT72L13 datasheet(86/370 Pages) EXAR

86 / 370 page

XRT72L13

MULTIPLEXER/FRAMER IC

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PRELIMINARY

REV. 1.0.6

contents, on the Address Bus pins, A[8:0], into

the XRT 72L13 DS3 Framer Microprocessor

Interface block. At this point, the "initial"

address of the "burst access" has now been

selected.

NOTE: The ALE_AS input pin should remain "low" for the

remainder of this "Burst I/O Access" operation.

A.5

Next, the µC/µP should indicate that this cur-

rent bus cycle is a "Write" operation by keeping

the RdB_DS pin "high" and toggling the

WRB_RW (Write Strobe) pin "low". This action

also enables the "bi-directional" data bus input

drivers of the Framer device.

A.6

The µC/µP places the byte (or word) that it

intends to write into the "target" register on the

"bi-directional data" bus, D[7:0].

A.7

After waiting the appropriate amount of time, for

the data (on the bi-directional data bus) to set-

tle, the µC/µP should toggle the WRB_RW

(Write Strobe) input pin "high". This action

accomplishes two things.

a. It latches the contents of the bi-directional data

bus into the XRT 72L13 DS3 Framer Micropro-

cessor Interface Block.

b. It terminates the write cycle.

Figure 40 presents a timing diagram which illustrates

the behavior of the Microprocessor Interface signals,

during the "initial" write operation within a Burst Ac-

cess, for an "Intel-type" µC/µP.

At the completion of this initial write cycle, the µC/µP

has written a byte or word into the first register or

buffer location (within the XRT 72L13 DS3 Framer) for

this particular burst access operation. In order to il-

lustrate this point, the byte (or word) of data, that is

being written in Figure 40 has been labeled "Data to

be Written (Offset = 0x00)".

2.2.2.2.1.2.2

The Subsequent Write Operations

The procedure that the µC/µP must use to perform

the remaining write cycles, within this burst access

operation, is presented below.

B.0

Execute each subsequent write cycle, as

described in steps B.1 through B.3.

B.1

Without toggling the ALE_AS input pin (e.g.,

keeping it "low"); apply the value of the next

FIGURE 40. BEHAVIOR OF THE MICROPROCESSOR INTERFACE SIGNALS, DURING THE "INITIAL" WRITE OPERATION

OF A

BURST CYCLE (INTEL-TYPE PROCESSOR)

ALE_AS

A[8:0]

CS*

D[7:0]

WRB_RW

Data to be Written (Offset = 0x00)

Address of “Initial” Target Register (Offset = 0x00)

RdB_DS

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