XRT72L13 datasheet(85/370 Pages) EXAR

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M13 MULTIPLEXER/CLEAR CHANNEL DS3 FRAMER IC

XRT72L13

PRELIMINARY

REV. 1.0.6

terminates the "Read" cycle by toggling the

RdB_DS (Read Strobe) input pin "high".

For subsequent read operations, within this burst cy-

cle, the µC/µP simply repeats steps 1 through 3, as il-

lustrated in Figure 39.

In addition to the behavior of the Microprocessor In-

terface signals, Figure 39 also illustrates other points

regarding the "Burst Access Operation".

a. The Framer internally increments the address

value, from the original "latched" value shown in

Figure 38. This is illustrated by the data, appear-

ing on the data bus, (for the first read access)

being labeled "Valid Data at Offset = 0x01"; and

that for the second read access being labeled

"Valid Data at Offset = 0x02.".

b. The Framer performs this "address incrementing"

process even though there are no changes in the

Address Bus Data, A[8:0].

2.2.2.2.1.1.3

Terminating the Burst Access

Operation

The Burst Access Operation will be terminated upon

the rising edge of the ALE_AS input signal. At this

point the Framer will cease to internally increment the

"latched" address value. Further, the µC/µP is now

free to execute either a "Programmed I/O" access or

to start another "Burst Access" Operation with the

XRT 72L13 DS3 Framer.

2.2.2.2.1.2

The "Intel-Mode" Write Burst

Access

Whenever an "Intel-type" µC/µP wishes to write data

into a "contiguous" range of addresses, then it should

do the following.

a. Perform the initial "write" operation; of the burst

access.

b. Perform the remaining "write" operations, of the

burst access.

c. Terminate the burst access operation.

Each of these "operations" within the burst access

are described below.

2.2.2.2.1.2.1

The Initial Write Operation

The initial write operation of an "Intel-type" Write

Burst Access is accomplished by executing a "Pro-

grammed I/O" write cycle as summarized below.

A.0

Execute a Single Ordinary (Programmed I/

O) Write cycle, as described in Steps A.1

through A.7 below.

A.1

Place the address of the "initial" target register

(or buffer location) within the Framer, on the

Address Bus pins, A[8:0].

A.2

A.2 At the same time, the "Address-Decoding"

circuitry (within the user's system) should

assert the CS* (Chip Select) input pin of the

Framer, by toggling it "low". This step enables

further communication between the µC/µP and

the Framer Microprocessor Interface block.

A.3

Assert the ALE_AS (Address Latch Enable)

input pin "high". This step enables the Address

Bus input drivers, within the Microprocessor

Interface Block of the Framer.

A.4

After allowing the data on the Address Bus pins

to settle (by waiting the appropriate "Address

Setup" time); the µC/µP should then toggle the

ALE_AS input pin "low". This step latches the

FIGURE 39. BEHAVIOR OF THE MICROPROCESSOR INTERFACE SIGNALS, DURING SUBSEQUENT "READ" OPERA-

TIONS WITHIN THE

BURST I/O CYCLE

ALE_AS

RDB_DS

A[8:0]

CS*

D[15:0]

Rdy_Dtck

Not Valid

Valid Data at Offset =0x01

WRB_RW

Not Valid

Valid Data at Offset =0x02

Address of “Initial” Target Register (Offset = 0x00)

XRT72L13 Datasheet(PDF) 85 Page - Exar Corporation

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