XRT72L13 datasheet(67/370 Pages) EXAR

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M13 MULTIPLEXER/CLEAR CHANNEL DS3 FRAMER IC

XRT72L13

PRELIMINARY

REV. 1.0.6

When the XRT72L13 has been configured to operate

in the "Multiplexer/De-Multiplexer Mode, then the chip

will function as follows.

1.1.1

In the Transmit Direction

When the XRT72L13 is operating the "Multiplexer/De-

Multiplexer" Mode, it consist of the following blocks.

• Seven (7) M12 MUXes.

• An M23 MUX.

• The Clear Channel DS3 Framer Block.

1.1.1.1

Operation of the M12 MUX

Each M12 MUX can be configured to accept either 4

DS1 signals, 3 E1 signals or a DS2 signal. Whenever

a given M12 MUX is configured to operate in the

“DS1” Mode, then it will accept four (4) DS1 signals

(via the “TxDS1Data_n” input pins) and it will multi-

plex these DS1 signals into a DS2 signal.

Whenever a given M12 MUX is configured to operate

in the “ITU-T G.747” Mode, then it will accept three

(3) E1 signals (via 3 out of 4 of the “TxDS1_n” input

pins) and it will multiplex these E1 signals into an

“ITU-T G.747” signal.

Finally, whenever a given M12 MUX is configured to

operate in the “DS2 Pass-Thru” Mode, then it will ac-

cept a DS2 signal (via one of the “TxDS1Data_n” in-

put pins) and will route these signals to the M23

MUX.

Each M12 MUX also consists of a “Transmit DS2” or

“ITU-T G.747 Framer” block. As the M12 MUX out-

puts its DS2 or ITU-T G.747 data stream to the “M23

MUX” then the “Transmit DS2/G.747 Framer” block

will do the following.

• Encapsulate the composite data stream (derived

from 4 DS1 signals) into an outbound DS2 framing

structure.

• Set the “Cxx” bits to the appropriate values in order

to indicate whether or not a bit-stuff event occurred

when creating this particular DS2 frame.

FIGURE 26. FUNCTIONAL BLOCK DIAGRAM OF THE XRT72L13 M13 MULTIPLEXER/FRAMER IC, WHILE OPERATING

IN THE

"MULTIPLEXER/DE-MULTIPLEXER MODE

Clear Channel

DS3 Framer

Clear Channel

DS3 Framer

Microprocessor

Interface

Microprocessor

Interface

M12

MUX

M12

DEMUX

M23

MUX

M23

DEMUX

TxDS1[0: 27]

TxClk[0:27]

RxDS1[0: 27]

RxClk[0:27]

DS2 or G.747

Data Streams

RxPOS

RxNEG

TxPOS

TxNEG

RxLineClk

TxLineClk

32/64 Bit

De-Jitter

FIFO

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