XRT72L13 datasheet(90/370 Pages) EXAR

90 / 370 page

XRT72L13

MULTIPLEXER/FRAMER IC

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PRELIMINARY

REV. 1.0.6

A.6

The µC/µP should then place the byte or word

that it intends to write into the "target" register,

on the bi-directional data bus, D[7:0].

A.7

Next, the µC/µP should initiate the bus cycle by

toggling the RdB_DS (Data Strobe) input pin

"low". When the XRT 72L13 DS3 Framer

senses that the WRB_RW input pin is "low",

and that the RdB_DS input pin has toggled

"low" it will enable the "input drivers" of the bi-

directional data bus, D[7:0].

A.8

After waiting the appropriate amount of time, for

this newly placed data to settle on the bi-direc-

tional data bus( e.g., the "Data Setup" time) the

Framer will assert the Rdy_Dtck (DTACK) out-

put signal.

A.9

After the µP/µC detects the Rdy_Dtck signal

(from the Framer) it should toggle the RdB_DS

input pin "high". This action accomplishes two

things:

a. It latches the contents of the bi-directional data

bus into the XRT 72L13 DS3 Framer Micropro-

cessor Interface block.

b. It terminates the "Write" cycle.

Figure 44 presents a timing diagram which illustrates

the behavior of the Microprocessor Interface signals,

during the "Initial" write operation within a Burst Ac-

cess, for a "Motorola-type" µC/µP.

At the completion of this initial write cycle, the µC/µP

has written a byte or word into the first register or

buffer location (within the XRT 72L13 DS3 Framer) for

this particular burst I/O access. In order to illustrate

how this "burst I/O cycle" works, the byte (or word) of

data, that is being written in Figure 44 has been la-

beled "Data to be Written (Offset = 0x00)."

2.2.2.2.2.2.2

The Subsequent Write Operations

The procedure that the µC/µP must use to perform

the remaining write cycles, within this burst access

operation, is presented below.

B.0

Execute each subsequent write cycle, as

described in Steps B.1 through B.3

B.1

Without toggling the ALE_AS (Address Strobe)

input pin (e.g., keeping it "high"); apply the

value of the next byte or word (to be written into

the Framer) to the bi-directional data bus pins,

D[7:0].

B.2

Toggle the RdB_DS (Data Strobe) input pin

"low". This step accomplishes the following.

a. The Framer internally increments the "latched

address" value (within the Microprocessor Inter-

face).

b. The input drivers of the bi-directional data bus are

enabled.

NOTE: In order to insure that the XRT 72L13 DS3 Framer

will interpret this signal as being a "Write" signal, the

µC/

µP should keep the WRB_RW input pin "low".

B.3

After some settling time, the data, in the inter-

nal data bus, will stabilize and is ready to be

latched into the Framer Microprocessor Inter-

face block. The Microprocessor Interface block

will indicate that this data is ready to be latched

by asserting the Rdy_Dtck (DTACK) output sig-

nal. At this point, the µC/µP should latch the

data into the Framer by toggling the RDB_DS

input pin "high".

FIGURE 44. BEHAVIOR OF THE MICROPROCESSOR INTERFACE SIGNALS, DURING THE "INITIAL" WRITE OPERATION

OF A

BURST CYCLE (MOTOROLA-TYPE PROCESSOR)

ALE_AS

A[8:0]

CS*

D[15:0]

RDB_DS

Rdy_Dtck

Data to be Written (Offset = 0x00)

Address of “Initial” Target Register (Offset = 0x00)

XRT72L13 Datasheet(PDF) 90 Page - Exar Corporation

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