XRT72L13 datasheet(23/370 Pages) EXAR

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XRT72L13

M13 MULTIPLEXER/CLEAR CHANNEL DS3 FRAMER IC

PRELIMINARY

REV. P1.0.6

RxDS1Data_2/

RxHDLC_Data_2

Receive DS1/E1 Data Output - Channel 2/Receive HDLC Control-

ler Block Output - Bit 2

The funtion of this output pin depends upon whether the XRT72L13 is

operating in the "Multiplexer/De-Multiplexer" Mode or in the "High

Speed HDLC Controller" Mode.

Receive DS1 Data Output - Channel 2 (Multiplexer/De-Multiplexer

Mode)

This pin outputs either a DS1 or E1 signal from the M12 multiplexer.

Each bit, within the DS1 or E1 data stream is output upon the rising

edge of RxDS1Clk_2.

Receive HDLC Controller Block Output - Bit 2 (High Speed HDLC

Controller Mode)

This output pin along with RxHDLC_Data[0:1] and

RxHDLC_Data[3:7] output the contents of all HDLC frames that have

been received (via the DS3 payload) from the remote terminal equip-

ment.

The data on this output pin is updated upon the rising edge of "RxH-

DLCClk".

NOTE: This pin is inactive while the Receive HDLC Controller is

receiving the "Flag Sequence" octet.

RxDS1Clk_2/

ValidFCS

Receive DS1/E1 Clock Output - Channel 2/Valid FCS Indicator

Output :

The funtion of this output pin depends upon whether the XRT72L13 is

operating in the "Multiplexer/De-Multiplexer" Mode or in the "High

Speed HDLC Controller" Mode.

Receive DS1 Clock Output - Channel 2 (Multiplexer/De-Multi-

plexer Mode)

This pin outputs either a DS1 (1.544MHz) or an E1 (2.048MHz) clock

signal to the Terminal Equipment. The XRT72L13 will update the data

on the "RxDS1Data_2" line, upon the rising edge of this signal.

Valid FCS Indicator Output - (High Speed HDLC Controller Mode)

This output pin is driven "high" anytime the Receive HDLC Controller

block has received an HDLC frame with a valid FCS value.

RxDS1Data_1/

RxHDLC_Data_1

Receive DS1/E1 Data Output - Channel 1/Receive HDLC Control-

ler Block Output - Bit 1:

The funtion of this output pin depends upon whether the XRT72L13 is

operating in the "Multiplexer/De-Multiplexer" Mode or in the "High

Speed HDLC Controller" Mode.

Receive DS1 Data Output - Channel 1: (Multiplxer/De-Multiplexer

Mode):

This pin outputs either a DS1 or E1 signal from the M12 multiplexer.

Each bit, within the DS1 or E1 data stream is output upon the rising

edge of RxDS1Clk_1.

Receive HDLC Controller Block Output - Bit 1 (High Speed HDLC

Controller Mode)

This output pin along with RxHDLC_Data_0 and RxHDLC_Data[2:7]

output the contents of all HDLC frames that have been received (via

the DS3 payload) from the remote terminal equipment.

The data on this output pin is updated upon the rising edge of "RxH-

DLCClk".

NOTE: This pin is inactive while the Receive HDLC Controller is

receiving the "Flag Sequence" octet.

PIN DESCRIPTIONS

PIN #NAME

TYPE

DESCRIPTION

XRT72L13 Datasheet(PDF) 23 Page - Exar Corporation

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