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DP8344 Datasheet(PDF) 124 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
Part # DP8344
Description  Biphase Communications Processor?좦CP
PDF  184 Pages
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Manufacturer  NSC [National Semiconductor (TI)]
Direct Link  http://www.national.com
Logo NSC - National Semiconductor (TI)

DP8344 Datasheet(HTML) 124 Page - National Semiconductor (TI)

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50 Device Specifications (Continued)
TABLE 5-25 Latched Write of IMEM (Notes 1 2)
Symbol
ID
Parameter
Formula
Min
Max
Units
tSU-RRW-CO
1
RAE REM-WR Falling before CLK-OUT Rising
24
ns
tH-RRW-CO
2
RAE REM-WR Rising after CLK-OUT Rising (Note 3)
THa
6ns
Tab20
ns
tH-RRW-X
3
RAE REM-WR Rising after XACK Rising
0
ns
tSU-CMD-RRW
4
CMD Valid before RAE REM-WR Falling
0
ns
tH-CMD-RRW
5
CMD Invalid after RAE REM-WR Falling
Ta
26
ns
tPD-RRW-X
6
RAE REM-WR Falling to XACK Falling
26
ns
tAZ-AAD-LCL
7
A AD Disabled before LCL Rising
TLab20
ns
tZA-LCL-AAD
8
A AD Enabled after LCL Falling
THab10
ns
tPD-RDAT-I
9
AD (Data) Valid to I Valid
30
ns
tH-RDAT-IWR
10
AD (Data) Invalid after IWR Rising
0
ns
tPD-RRW-WPND
11
RAE REM-WR Rising to WR-PEND Falling
5
Ta
34
ns
tPD-LCL-IA
12
LCL Falling to Next IA Valid
TaTHab19
5
ns
tZA-IWR-I
13
IWR Falling to I Enabled
Tab2ns
tAZ-IWR-I
14
IWR Rising to I Disabled
22
52
ns
tPD-I-IWR
15
I Valid before IWR Rising
(nIWa1)Tab18
ns
tPD-LCL-IWR
16
LCL Rising to IWR Falling
b
3ns
tPD-IWR-LCL
17
IWR Rising to LCL Falling
Tab17
ns
tW-IWR
18
IWR Low Time
(nIWa2)Tab12
ns
tSU-CMD-WPND
19
CMD Valid before WR-PEND Rising
16
ns
tH-CMD-WPND
20
CMD Invalid after WR-PEND Rising
4
ns
tPD-I-IA
21
I Disabled to IA Invalid
2TaTHab70
ns
tSU-RRWr-CO
22
RAE REM-WR Rising before CLK-OUT Rising
20
ns
tPD-X-WPND
23
XACK Rising to WR-PEND Rising
13
ns
Note 1
All parameters are individually tested and guaranteed Interpreting this data by numerically adding two or more parameters to create a new timing
specification may lead to invalid results
Note 2
Two remote writes to instruction memory are necessary to store a 16-bit instruction word to IMEMlow byte followed by high byte The timing of the 2nd
write is shown in the following diagram The first write is the same as a write of the PC or RIC as shown in
Figure 5-23
Note 3
The maximum value for this parameter is the latest RAE REM-WR can be removed without delaying the remote access by one T-state
124



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