DP8344 datasheet(131/184 Pages) NSC

131 / 184 page

60 Reference Section

61 INSTRUCTION SET REFERENCE

The Instruction Set Reference section contains detailed in-

formation on the syntax and operation of each BCP instruc-

tion The instructions are arranged in alphabetical order by

mnemonic for easy access Although this section is primarily

intended as a reference for the assembly language pro-

grammer previous assembly language experience is not a

prerequisite The intent of this instruction set reference is to

include all the pertinent information regarding each instruc-

tion on the page(s) describing that instruction The only ex-

ceptions to this rule concern the instruction addressing

modes and the bus timing diagrams The discussion of the

instruction addressing modes occurs at the beginning of the

BCP Instruction Set Overview section and therefore will

not be repeated here The figures for the bus timing dia-

grams are located at the end of this introduction rather than

constantly repeating them under each instruction The infor-

mation that is contained under each instruction is divided

into eight categories titled Syntax Affected Flags Descrip-

tion Example Instruction Format T-states Bus timing and

Operation The following paragraphs explain what informa-

tion each category conveys and any special nomenclature

that a category may use

Syntax

This category illustrates the assembler syntax for each in-

struction Multiple lines are used when a given instruction

supports more than one type of addressing mode or if it has

an optional mnemonic All capital letters commas () math

symbols (a b) and brackets (

) are entered into the as-

sembler exactly as shown Braces (

) surround an instruc-

tion’s optional operands and their associated syntax The

text between the braces may either be entered in with or

omitted from the instruction The braces themselves should

not be entered into the assembler because they are not part

of the assembler syntax Lower case characters and oper-

ands that begin with the capital R represent symbols These

must be replaced with actual register names numbers or

equated registers and numbers Table 6-1 lists all the sym-

bols and their associated meanings

Affected Flags

If an instruction sets or clears any of the ALU flags (ie

Negative N

Zero Z

Carry C

andor Overflow V )

then those flags affected are listed under this category

Description

The Description category contains a verbal discussion

about the operation of an instruction the operands it allows

and any notes highlighting special considerations the pro-

rammer should keep in mind when using the instruction

Example

Each instruction has one or more coding examples de-

signed to show its typical usage(s) For clarity register

name abbreviations are often used instead of the register

numbers (ie RTR is used in place of R4) Each example

assumes that the ‘‘EQU’’ assembler directive has been pre-

viously executed to establish these relationships Informa-

tion relating register abbreviations to register names num-

bers and purpose is located in the CPU Registers section

Instruction Format

This category illustrates the formation of an instruction’s

machine code for each operand variation Assembly or dis-

assembly of any instruction can be accomplished using

these figures

T-states

The T-state category lists the number of CPU clock cycles

required for each instruction including operand variations

and conditional considerations Using this information actu-

al execution times may be calculated For example if the

conditional relative jump instruction’s condition is not met

the CPU’s clock cycle is 18867 MHz ( CCS e0) and no

instruction wait states are requested ( IW1b0 e00) then

Jcc’s execution time is calculated as shown below

texecution e 1(CPU clock frequency) c T-states

1(18867 c 106 Hz) c 2

(53 c 10b9s) c 2

106 ns

See the section BCP Timing for more information on calcu-

lating instruction execution times

Bus Timing

This category refers the user to the Bus Timing

Figures 6-1

6-6 on the following pages These figures illustrate the

relationship between software instruction execution and

some of the BCP’s hardware signals

Operation

The operation category illustrates each instruction’s opera-

tion in a symbolic coding format Most of the operand

names used in this format come directly from each instruc-

tion’s syntax The exceptions to this rule deal with implied

operands Instructions that imply the use of the accumula-

tors use the name ‘‘accumulator’’ as an operand Instruc-

tions that manipulate the Program Counter use the symbol

‘‘PC’’ Instructions that ‘‘push’’ onto or ‘‘pop’’ off of the inter-

nal Address Stack specify ‘‘Address Stack’’ as an operand

Instructions that save or restore the ALU flags and the reg-

ister bank selections use those terms as operands Two

specialized operator symbols are used in the symbolic cod-

ing format the arrow ‘‘

x’’ and the concatenation operator

‘‘’’ The arrow indicates the movement of data from one

operand to another

For instance

after the operation

‘‘Rs

xRd’’ is performed the content of Rd has been re-

placed with the content of Rs The concatenation operator

‘‘’’ simply indicates that the operands surrounding an ‘‘’’

are attached together forming one new operand For exam-

ple ‘‘PC

GIE

ALU flags

ons

xAddress Stack’’ means that the Program Counter

the Global Interrupt Enable bit the ALU flags and the regis-

ter bank selections are combined into one operand and

pushed onto the internal Address Stack Three conditional

structures are utilized in the symbolic coding format the

‘‘Two Line If’’ structure the ‘‘Blocked If’’ structure and the

‘‘Blocked Case’’ structure In the ‘‘Two Line If’’ structure if

the

condition is met then the operation is performed other-

wise the

operation is not performed

‘‘Two Line If’’ structure

condition

then

operation

131

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