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DP8344 Datasheet(PDF) 132 Page - National Semiconductor (TI) |
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DP8344 Datasheet(HTML) 132 Page - National Semiconductor (TI) |
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132 / 184 page ![]() 60 Reference Section (Continued) In the ‘‘Blocked If’’ structure if the condition is met then all the operations between the ‘‘If’’ statement and the ‘‘End if’’ statement are performed ‘‘Blocked If’’ structure If condition then operation operation etc End if In the ‘‘Blocked Case’’ structure the operation preceded by the equivalent numeric value of the operand is executed For example if the operand’ s value is equal to ‘‘1’’ then the operation preceded by ‘‘1’’ is executed ‘‘Blocked Case’’ structure Case operand of 0 operation 1 operation 2 etc End case Two reference tables have been added to the back of the Instruction Set Reference section The first table Table 6-2 lists all the instructions with their associated T-states Af- fected Flags and Bus Timing figure numbers in a compact format The second table Table 6-3 lists all the instructions in opcode order to facilitate disassembly TABLE 6-1 Notational Conventions for Instruction Set Symbol Represents Meaning Length n 0 to 255 Unsigned Number 8 Bits a 127 to b128 Signed Number nn 0 to 65535 Unsigned Number 16 Bits Rs R0 – R31 Source Register Rd R0 – R31 Destination Register Rsd R0 – R31 Combination SourceDestination Register rs R0 – R15 Limited Source Register rd R0 – R15 Limited Destination Register rsd R0 – R15 Limited Combination SourceDestination Register Ir IW IX IY IZ Index Register mIr Index Register in One of the Following Address Modes Irb Post Decrement Ir No Change Ira Post Increment a Ir Pre-Increment b 0 – 7 Shift Field 3 Bits m 0 – 7 Mask Field 3 Bits p 0 – 7 Position Field 3 Bits s 0 – 1 State Field 1 Bit f 0 – 7 Flag Reference Field 3 Bits cc Condition Code Instruction Extensions v 0 – 63 Vector Field 6 Bits g 0 – 3 Global Interrupt Enable Flag GIE Status Control 2 Bits g 0 – 1 Global Interrupt Enable Flag GIE Limited Status Control 1 Bit rf 0 – 1 Register Bank and ALU Flag Status Control 1 Bit ba 0 – 1 Register Bank A Select 1 Bit bb 0 – 1 Register Bank B Select 1 Bit 132 |
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