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FDC37M607 Datasheet(PDF) 164 Page - SMSC Corporation |
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FDC37M607 Datasheet(HTML) 164 Page - SMSC Corporation |
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164 / 182 page  164 FIGURE 12B - EPP 1.9 DATA OR ADDRESS WRITE CYCLE TIMING NAME DESCRIPTION MIN TYP MAX UNITS t1 nIOW Asserted to PDATA Valid 0 50 ns t2 nWAIT Asserted to nWRITE Change (Note 1) 60 185 ns t3 nWRITE to Command Asserted 5 35 ns t4 nWAIT Deasserted to Command Deasserted (Note 1) 60 190 ns t5 nWAIT Asserted to PDATA Invalid (Note 1) 0 ns t6 Time Out 10 12 µs t7 Command Deasserted to nWAIT Asserted 0 ns t8 SDATA Valid to nIOW Asserted 10 ns t9 nIOW Deasserted to DATA Invalid 0 ns t10 nIOW Asserted to IOCHRDY Asserted 0 24 ns t11 nWAIT Deasserted to IOCHRDY Deasserted (Note 1) 60 160 ns t12 IOCHRDY Deasserted to nIOW Deasserted 10 ns t13 nIOW Asserted to nWRITE Asserted 0 70 ns t14 nWAIT Asserted to Command Asserted (Note 1) 60 210 ns t15 Command Asserted to nWAIT Deasserted 0 10 µs t16 PDATA Valid to Command Asserted 10 ns t17 Ax Valid to nIOW Asserted 40 ns t18 nIOW Asserted to Ax Invalid 10 ns t19 nIOW Deasserted to nIOW or nIOR Asserted 40 ns t20 nWAIT Asserted to nWRITE Asserted (Note 1) 60 185 ns t21 nWAIT Asserted to PDIR Low 0 ns t22 PDIR Low to nWRITE Asserted 0 ns Note 1: nWAIT must be filtered to compensate for ringing on the parallel bus cable. WAIT is considered to have settled after it does not transition for a minimum of 50 nsec. |
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