FDC37M607 datasheet(101/182 Pages) SMSC

101 / 182 page

101

not be asserted for more than 32 DMA cycles in

a row.

After the 32nd cycle, PDRQ must be

kept unasserted until nPDACK is deasserted for

a minimum of 350nsec. Note: The only way to

properly terminate DMA transfers is with a TC.

DMA may be disabled in the middle of a transfer

by first disabling the host DMA controller. Then

setting serviceIntr to “1”, followed by setting

dmaEn

to “0”, and waiting for the FIFO to

become empty or full. Restarting the DMA is

accomplished by enabling DMA in the host,

setting

dmaEn

to “1”, followed by setting

serviceIntr to “0”.

DMA Mode - Transfers from the FIFO to the

Host

(Note: In the reverse mode, the peripheral may

not continue to fill the FIFO if it runs out of data

to transfer, even if the chip continues to request

more data from the peripheral.)

The ECP activates the PDRQ pin whenever

there is data in the FIFO. The DMA controller

must respond to the request by reading data

from the FIFO.

The ECP will deactivate the

PDRQ pin when the FIFO becomes empty or

when

the

becomes

true

(qualified

nPDACK), indicating that no more data is

required.

PDRQ goes inactive after nPDACK

goes active for the last byte of a data transfer

(or on the active edge of nIOR, on the last byte,

if no edge is present on nPDACK).

If PDRQ

goes inactive due to the FIFO going empty, then

PDRQ is active again as soon as there is one

byte in the FIFO. If PDRQ goes inactive due to

the TC, then PDRQ is active again when there

is one byte in the FIFO, and serviceIntr has

been re-enabled.

Note: A data underrun may

occur if PDRQ is not removed in time to prevent

an unwanted cycle.

Programmed I/O Mode or Non-DMA Mode

The ECP or parallel port FIFOs may also be

operated using interrupt driven programmed I/O.

Software can determine the writeIntrThreshold,

readIntrThreshold, and FIFO depth by accessing

the FIFO in Test Mode.

Programmed I/O transfers are to the ecpDFifo

at 400H and ecpAFifo at 000H or from the

ecpDFifo located at 400H, or to/from the tFifo at

400H.

To use the programmed I/O transfers,

the host first sets up the direction and state, sets

dmaEn to 0 and serviceIntr to “0”.

The ECP requests programmed I/O transfers

from the host by activating the PINTR pin. The

programmed I/O will empty or fill the FIFO using

the appropriate direction and mode.

Note: A threshold of 16 is equivalent to a

threshold of 15.

These two cases are treated

the same.

Programmed I/O - Transfers from the FIFO to

the Host

In the reverse direction an interrupt occurs when

serviceIntr

is 0 and

readIntrThreshold bytes

are available in the FIFO.

If at this time the

FIFO is full

it can be emptied completely in a

single burst, otherwise readIntrThreshold bytes

may be read from the FIFO in a single burst.

readIntrThreshold =(16-<threshold>) data bytes

in FIFO

An interrupt is generated when serviceIntr is 0

and the number of bytes in the FIFO is greater

than or equal to (16-<threshold>). (If the

threshold = 12, then the interrupt is set

whenever there are 4-16 bytes in the FIFO). The

PINT pin can be used for interrupt-driven

systems. The host must respond to the request

by reading data from the FIFO. This process is

repeated until the last byte is transferred out of

FDC37M607 Datasheet(PDF) 101 Page - SMSC Corporation

FDC37M607 Datasheet(HTML) 101 Page - SMSC Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL