AD9545 datasheet(109/157 Pages) AD

109 / 157 page

Data Sheet

AD9545

Rev. A | Page 109 of 157

TIME TO DIGITAL CONVERTER (TDC)

Time to digital converters (TDCs) are at the core of the DPLL

technology in the AD9545. The purpose of a TDC is to

continuously observe a clock signal, note the occurrence of an

edge transition, and generate a digital time stamp identifying

when the edge occurred.

Because a TDC effectively digitizes rising edge clock events by

means of time stamps, it enables digital (that is, numeric)

processing of clock signals. In a conventional PLL, for example,

a PFD circuit measures the relative phase of the reference and

feedback signals and provides an analog representation of the

phase difference. Instead of an analog representation of the

phase difference, the AD9545 uses a pair of TDCs (one in the

reference path and one in the feedback path) to generate

reference and feedback time stamps, constituting a numeric

representation of the phase difference. With phase information

in numeric form, the AD9545 implements the entire PLL

function digitally by employing a digital PFD, digital loop filter

and a NCO.

Figure 87 shows a simplified diagram of a TDC. The TDC has a

time base clock (which gives the TDC its sense of time), an

input clock (the signal in question), and an output consisting of

numeric time stamps.

TIME STAMPS

ONE PER INPUT

CLOCK EDGE EVENT

TIME BASE CLOCK

INPUT CLOCK

TDC

Figure 87. TDC Diagram

The AD9545 contains eight TDCs:

•

Four associated with the four reference inputs at the output

of the reference dividers

•

Two associated with the two DPLLs at the output of the

feedback divider

•

Two auxiliary TDCs available to the user for general use

Each TDC produces digital time stamps identifying each rising

edge of its input clock. That is, the TDCs generate time stamps

at a rate commensurate with their respective input clock period.

It is up to the user, however, to ensure the TDC input clock rate

is within the specified range of 1 Hz to approximately 200 kHz.

The TDC time stamps derive from an internal time base that

originates with the device system clock. As such, the TDCs

benefit from the ability of the AD9545 to provide system clock

compensation, assuming the user activates system clock

compensation via Register 0x0280 to Register 0x0282 (see the

System Clock Compensation section).

AD9545 Datasheet(PDF) 109 Page - Analog Devices

AD9545 Datasheet(HTML) 109 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL