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AD9545 Datasheet(PDF) 107 Page - Analog Devices |
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AD9545 Datasheet(HTML) 107 Page - Analog Devices |
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107 / 157 page  Data Sheet AD9545 Rev. A | Page 107 of 157 TRANSLATION PROFILE x.y ENABLED? NO YES SOURCE = REFA, AA, B, BB? NO YES SOURCE = AUX. NCO0, NCO1? NO SOURCE = FEEDBACK FROM DPLL0 OR DPLL1 YES REFERENCE VALID? YES SOURCE DPLL IN FREERUN OR HOLDOVER MODE? YES SOURCE APLL CALIBRATED AND LOCKED? YES TRANSLATION PROFILE x.y = BUILD OUT? YES NO YES NO TRANSLATION PROFILE x.y = INTERNAL ZERO DELAY? APLLx CALIBRATED AND LOCKED? YES NO TRANSLATION PROFILE x. IS EXTERNAL ZERO DELAY DISTRIBUTION FEEDBACK PATH SYNCED (OR SYNC REQUESTED AWAITING TRIGGER)? DISTRIBUTION FEEDBACK CHANNEL NOT POWERED DOWN? YES NO YES SYSTEM CLOCK STABLE? YES NO NO NO NO EXTERNAL ZERO DELAY REFERENCE SOURCE VALID? YES NO NO REFERENCE SOURCE VALIDATION TRANSLATION PROFILE x.y VALID? YES NO NOTES 1. x = CHANNEL, y = PROFILE. TRANSLATION PROFILE VALIDATION Figure 85. Flowchart for Translation Profile Validation |
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