AD9545 datasheet(136/157 Pages) AD

Part #	AD9545

Description	Quad Input, 10-Output, Dual DPLL/IEEE 1588 1 pps Synchronizer and Jitter Cleaner

PDF	157 Pages

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Manufacturer	AD [Analog Devices]

Direct Link	http://www.analog.com

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136 / 157 page

AD9545

Data Sheet

Rev. A | Page 136 of 157

In addition, M0 is assigned for AND operation, M2 for NOT OR

operation, M3 for NOT AND operation, and M6 for OR operation

(that is, the 2-bit codes in Register 0x100 and Register 0x101

according to Table 61).

With these settings, the input/output (I/O) update function

behaves according to the following Boolean equation:

I/O update = ((NOT M2) OR M6) AND M0 AND (NOT M3)

In this case, an I/O update occurs when M0 is Logic 1 and M3 is

Logic 0, and either M2 is Logic 0 or M6 is Logic 1.

When an Mx control pin acts on a control function individually

(rather than as part of a group, per the previous example), the

Boolean functionality of the codes in Table 61 reduces to two

possibilities. Namely, Code 00 and Code 10 specify a Boolean

true (the Mx pin logic state applies to the corresponding control

function directly), whereas Code 01 and Code 11 specify a

Boolean false (the Mx pin logic state applies to the corresponding

control function with a logical inversion).

AD9545 Datasheet(PDF) 136 Page - Analog Devices