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Data Sheet

AD9545

Rev. A | Page 133 of 157

Table 57. Compensation Rate Limiting

Binary Value of the Slew Rate Limit Bit Field

Rate Limit

000

None

001

0.715

010

1.430

011

2.860

100

5.720

101

11.44

110

22.88

111

45.76

Compensation Assignment Guidelines

When a user time stamp processor (see the User Access to Time

Stamps section) is in use, the auxiliary NCO associated with

that user time stamp processor as well as the time stamp source

to that user time stamp processor must both use the same

COMPx factor. That is, the user must program identical values

in the bit field of the REFx/auxiliary TDC compensation

destination associated with the user time stamp processor

source and in the bit field of the auxiliary NCO 0 (or auxiliary

NCO 1) compensation destination serving as the reference time

source for the user time stamp processor (see Figure 104).

To avoid a positive feedback loop in the integrated

compensation subsystem, do not assign COMPx sources

involving CF2 in Table 56 to the following compensation

destinations:

•

DPLL0 NCO compensation destination when the DPLL

channel error source bit is Logic 0

•

DPLL1 NCO compensation destination when the DPLL

channel error source bit is Logic 1

Likewise, do not assign COMPx sources involving CF3 in Table 56

to the auxiliary DPLL.

SYSTEM CLOCK COMPENSATION PROGRAMMING

REGISTERS

System clock compensation comprises three compensation

methods and six compensation destinations. Three 8-bit

registers constitute the function of the distributor in Figure 103.

The three registers function as a connection matrix with six

3-bit fields distributed over the three registers (see Figure 104).

Each 3-bit field associates with one of the six compensation

destinations:

•

Auxiliary DPLL

•

REFX TDCs and auxiliary TDCs

•

Auxiliary NCO 0

•

Auxiliary NCO 1

•

DPLL 0

•

DPLL 1

The value of the 3-bit field for a given destination establishes

the COMPx factor applied to that destination (see the Integrated

Compensation Subsystem section for details).

The compensation methods relate to columns in the bit field

matrix of Figure 104, whereas the compensation destinations

relate to rows. Organizing the compensation bit field matrix in

this way enables any compensation destination to receive any

one of the eight possible COMPx signals (see Figure 103).

Certain compensation destinations have constraints on which

compensation methods apply (see the Compensation

Assignment Guidelines section).

To provide system clock compensation to Auxiliary NCO 0, use

a combination of Compensation Method 1 and Compensation

Method 3.

First, determine the appropriate compensation destination bit

field per Figure 104. In this case, Bits[D2:D0] of Register 0x0281

applies because the compensation destination is auxiliary NCO 0.

Next, determine the 3-bit code to write to Bits[D2:D0] of Register

0x0281 per the leftmost column of Table 56 corresponding to the

appropriate COMPx. In this case, the code is 5 (101 binary) because

it uses CF1 and CF3 per the middle column of Table 56. In

conclusion, by programming Bits[D2:D0] = 5 in Register 0x0281,

auxiliary NCO 0 receives both Compensation Method 1 and

Compensation Method 3.

NOT USED

AUXILIARY DPLL NCO 1

COMPENSATION DESTINATION

DPLL 1 NCO

COMPENSATION DESTINATION

AUXILIARY DPLL NCO

COMPENSATION

DESTINATION

REFX/AUXILIARY TDC

COMPENSATION DESTINATION

AUXILIARY NCO 0

COMPENSATION DESTINATION

DATA

BITS

0x0280

0x0281

0x0282

CF3

CF2

CF1

CF3

CF2

CF1

NOT USED

DPLL 0 NCO

COMPENSATION DESTINATION

NOT USED

Figure 104. System Clock Compensation Registers

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