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AD9545 Datasheet(PDF) 129 Page - Analog Devices

Part # AD9545
Description  Quad Input, 10-Output, Dual DPLL/IEEE 1588 1 pps Synchronizer and Jitter Cleaner
PDF  157 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD9545 Datasheet(HTML) 129 Page - Analog Devices

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Data Sheet
AD9545
Rev. A | Page 129 of 157
Therefore,
T3 Exponent = C3_ExpVal = −28
= 0xE4 (hexadecimal)
T3 Significand = round(C3 × 215 – C3_ExpVal)
= round(2.2493907 × 10−9 × 215 − (−28))
= 19,786
= 0x4D4A (hexadecimal)
Using C4 as an example, convert Coefficient C4 = 2.7943570 ×
10−11 to its corresponding bit field values. First, check that C4 is
greater than the quantization limit.
C4_ExpVal =
1
2
log
|
log
4
+
C
=
1
2
log
|
10
7943570
.
2
|
log
11
+
×
−
= −35
This is above the quantization limit of −127, therefore
T4 Exponent = C4_ExpVal = −35
= 0xDD (hexadecimal)
T4 Significand = round(C4 × 215 − C4_ExpVal)
= round(2.7943570 × 10−11 × 215 − (−35))
= 31,462
= 0x7AE6 (hexadecimal)
Using C5 as an example, convert Coefficient C5 = −2.4817310 ×
10−13 to its corresponding bit field values. First, check that C5 is
above the quantization limit.
C5_ExpVal =
1
2
log
|
log
5
+
C
=
1
2
log
10
4817310
.
2
|
log
13
+
×
−
−
= −41
This value is greater than the quantization limit of −127.
Therefore,
T5 Exponent = C5_ExpVal = −41
= 0xD7 (hexadecimal)
T5 Significand = round(C5 × 215 − C5_ExpVal)
= round(−2.4817310 × 10−13 × 215 − (−41))
= −17883
= 0xBA25 (hexadecimal)
Use the following formulas to verify the value of the bit field
computations closely matches the desired coefficient value;
CD
= Constant compensation value × 2−45
(26)
Cx|x ≠ D = Tx significand × 2Tx exponent – 15
(27)
Note that there may be a slight difference between the values
produced by Equation 26 and Equation 27 and the original
coefficient values due to quantization effects.
Example (coefficient verification)
C0 = 35,349,513,305 × 2−45
= 1.004694 × 10-3 (verified)
C1 = −24,849 × 2−18−15
= −2.892804 × 10−6 (verified)
C2 = −26,265 × 2−22−15
= −1.911030 × 10−14 (verified)
C3 = 19,786 × 2−28−15
= 2.249408 × 10−9 (verified)
C4 = 31,462 × 2−35−15
= 2.794387 × 10−11 (verified)
C5 = −17,883 × 2−41−15
= −2.481765 × 10−13 (verified)
Digital Filter
The CF1 values produced by the polynomial calculator block in
Figure 99 depend on temperature measurements (internal or
external) as an input parameter. Any noise associated with those
measurements is a potential noise source on CF1, which can
lead to a degradation of phase noise performance. To mitigate
potential noise injection by the compensation mechanism,
Compensation Method 1 employs a filter that applies a
smoothing function to the raw CF1 values.
The user controls the filter bandwidth via the 3-bit unsigned
coefficient output filter cutoff bit field in Bits[D2:D0] of
Register 0x0288 according to Table 54. The filter comprises two
colocated poles that yield a 3 dB bandwidth per Table 54.
Table 54. Digital Filter Bandwidth
Binary Value
3 db Bandwidth (Hz)
000
156
001
78
010
39
011
20
100
10
101
5
110
2
111
1
The device automatically bypasses the digital filter under the
following conditions:
•
The system clock is unstable
•
The difference between the input and output of the digital
filter exceeds ~125 ppm.
None of these conditions occur during normal operation; thus,
the filter is nearly always present.



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