AD9545 datasheet(131/157 Pages) AD

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Data Sheet

AD9545

Rev. A | Page 131 of 157

SYSTEM

CLOCK

SOURCE

fSRC

STABLE

FREQUENCY

SOURCE

XOA XOB

SYSTEM

CLOCK PLL

FTW

DIGITAL

PHASE

DETECTOR

FTW

ANALYZER

AUXILIARY DPLL

fNCO

CF3

REFERENCE

MONITOR

REFx NOMINAL PERIOD

AUXILIARY x PERIOD

AUXILIARY DPLL

BANDWIDTH

COMPx

LOCK

DETECTOR

DIGITAL

LOOP

FILTER

NCO

fREF

AD9545

REFERENCE

DIVIDER

AND TDC

Figure 102. Compensation Method Number 3

Auxiliary DPLL Loop Bandwidth

The user controls the loop bandwidth of the auxiliary DPLL

servo loop via the unsigned 16-bit auxiliary DPLL bandwidth

bit field in Register 0x0285 to Register 0x0286. The loop

bandwidth of the auxiliary DPLL is 0.1 Hz scaled by the value of

the auxiliary DPLL bandwidth bit field.

Given a desired loop bandwidth of 247.63 Hz, determine the

appropriate value of the auxiliary DPLL bandwidth bit field by

the following:

Auxiliary DPLL Bandwidth = (247.63 Hz)/(0.1 Hz)

= 2476 (nearest integer)

= 0x09AC (hexadecimal)

The programmed bandwidth affects how long it takes the

auxiliary DPLL to lock to the stable reference: the lower the

bandwidth, the longer it takes the auxiliary DPLL to lock. The

programmed bandwidth also affects the ability of the auxiliary

DPLL to track variations of the system clock frequency.

Specifically, a relatively stable, slowly varying system clock

frequency allows the use of a low loop bandwidth, whereas a

system clock exhibiting more rapid frequency variations

requires a wider loop bandwidth. For example, using an OCXO

as the system clock reference allows the use of a 0.1 Hz loop

bandwidth, whereas a standard crystal oscillator necessitates a

loop bandwidth in excess of 50 Hz.

Auxiliary DPLL Status

The auxiliary DPLL has a dedicated reference monitor to

provide indication that the reference period is within limits.

The reference monitor relies on user input of the expected

reference period via the appropriate REFx nominal period or

Auxiliary x period bit fields. The reference monitor status is

available via the auxiliary DPLL unfaulted and auxiliary DPLL

faulted bits in Bits[D3:D2] of Register 0x300C or via the

auxiliary DPLL reference fault bit in Bit D2 of Register 0x3002.

The auxiliary DPLL has a builtin lock detector for indicating

lock status. The lock/unlock thresholds for the lock detector are

fixed and not user programmable. The lock detector status is

available via the auxiliary DPLL unlocked and auxiliary DPLL

locked bits in Bits[D1:D0] of Register 0x300C or via the

auxiliary DPLL lock detect bit in Bit D1 of Register 0x3002.

Auxiliary DPLL Reference Monitor

Under normal conditions, the auxiliary DPLL continuously

updates CF3 computations with each rising edge event to the

TDC associated with the stable reference. Under certain

conditions, however, the auxiliary DPLL can enter a holdover

state, for example,

•

The user programs auxiliary DPLL bandwidth = 0

•

The reference period error exceeds ±1%

When the auxiliary DPLL is in the holdover state, it is

effectively in an open-loop condition (that is, the NCO output

is static). As such, the auxiliary DPLL holds the CF3 value that

existed just prior to entering the holdover state. Therefore, it is

not possible to ascertain further stability information until the

loop resumes normal operation. When the condition that

forced holdover no longer exists, however, the auxiliary DPLL

returns to closed-loop operation and resumes updating CF3

(that is, when the lock detector indicates a lock condition).

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