AD9545 datasheet(135/157 Pages) AD

135 / 157 page

Data Sheet

AD9545

Rev. A | Page 135 of 157

When the start-up conditions select the serial port to be I2C

mode (that is, M4 is Logic 1 at startup), the M5 and M6 pins

determine the I2C port device address offset, per Table 59. The

logic levels in Table 59 only apply during a power-up or reset

operation.

Table 59. I²C Device Address Offset

Address Offset

Not applicable

1001000 (0x48)

1001001 (0x49)

1001010 (0x4A)

1001011 (0x4B)

1 X means don’t care.

STATUS FUNCTIONALITY

Configuring an Mx pin as a status pin gives the user access to

specific internal device status/IRQ functions in the form of a

hardware pin that produces a logic signal. Each Mx pin has a

corresponding Mx function register. To assign an Mx pin as a

status pin, write a Logic 1 to the Mx output enable bit in the

corresponding Mx pin function register (Register 0x0102 to

To assign a specific status/IRQ function to an Mx pin configured as

a status pin, program the appropriate 7-bit code to Bits[D6:D0] of

the corresponding Mx function register. See the Interrupt Request

(IRQ) section for details regarding IRQ functionality.

When configured as a status pin, the output mode of an Mx pin

depends on a 2-bit mode code per Table 60. The 2-bit codes reside

in Register 0x100 through Register 0x101, where the 2-bit codes

constitute the Mx receiver/driver bit fields. The Mx receiver/driver

bit fields perform a different function when the Mx pin is a control

pin (see the Control Functionality section).

Table 60. Mx Receiver/Driver Bit Field Codes for Mx Status Pins

Code

Mode

Description

CMOS,

active high

Output is Logic 0 when deasserted and

Logic 1 when asserted (default operating

mode).

CMOS,

active low

Output is Logic 1 when deasserted and

Logic 0 when asserted.

PMOS,

open drain

Output is high impedance when deasserted

and active high when asserted.

NMOS,

open drain

Output is high impedance when deasserted

and active low when asserted.

The PMOS open-drain mode requires an external pull-down

resistor. The NMOS open-drain mode requires an external pull-up

resistor. The open-drain modes enable the implementation of

wire-OR’ed functionality of multiple Mx status pins (including

Mx status pins across multiple AD9545 devices or other compatible

devices—for example, to implement an IRQ bus).

The drive strength of an Mx status pin is programmable via the

corresponding Mx configuration bits (Bits[D6:D0] of the pin

drive strength register). Logic 0 (default) selects normal drive

strength (~6 mA) and Logic 1 selects weak drive strength (~3 mA).

CONTROL FUNCTIONALITY

Configuring an Mx pin as a control pin gives the user control of the

specific internal device functions via an external hardware logic

signal. Each Mx pin has a corresponding Mx function register. To

assign an Mx pin as a control pin, write a Logic 0 to the Mx output

enable bit in the corresponding Mx function register (Register

0x0102 to Register 0x0108).

To assign an Mx control pin to a specific function, program the

appropriate 7-bit code to Bits[D6:D0] of the corresponding Mx

function register. See the Interrupt Request (IRQ) section for

details regarding IRQ functionality.

When configured as an Mx control pin, the logical level applied to

the Mx pin translates to the selected device function. It is also

possible to assign multiple Mx control pins to the same control

function with the multiple pins implementing a Boolean expres-

sion. The Boolean operation associated with an Mx control pin

depends on a 2-bit code per Table 61. The 2-bit codes reside in

constitute the Mx receiver/driver bit fields. The Mx receiver/driver

bit fields perform a different function when the Mx pin is a status

pin (see the Status Functionality section).

Table 61. Mx Receiver/Driver Bit Field Codes for Mx Control

Pins

Code

Boolean

Description

AND

Logical AND the associated Mx control pin

with the other Mx control pins assigned to

the same control function.

NOT AND

Invert the logical state of the associated Mx

control pin and AND it with the other Mx

control pins assigned to the same control

function.

Logical OR the associated Mx control pin with

the other Mx control pins assigned to the

same control function.

NOT OR

Invert the logical state of the associated Mx

control pin and OR it with the other Mx control

pins assigned to the same control function.

The Boolean functionality of aggregated Mx control pins follows a

hierarchy whereby logical OR operations occur before logical AND

operations. The OR and NOT OR operations are collectively

grouped into a single result. A logical AND is then performed

using that result and the remaining AND and NOT AND

operations.

Consider a case where M0, M2, M3, and M6 are configured as

control pins and are assigned to the input/output update control

function; that is, Bits[D6:D0] = 0x01 in Register 0x0102,

AD9545 Datasheet(PDF) 135 Page - Analog Devices

AD9545 Datasheet(HTML) 135 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL