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AD9545

Data Sheet

Rev. A | Page 132 of 157

INTEGRATED COMPENSATION SUBSYSTEM

The three compensation methods comprise the integrated

compensation subsystem of the AD9545. The compensation

subsystem allows the user to employ any combination of the

three compensation methods to any of the NCOs and TDCs

within the AD9545 (barring a few exceptions per the

Compensation Assignment Guidelines section). Figure 103

shows a simplified block diagram of the compensation

subsystem.

The implied feedback path between DPLL0/DPLL1 and

Compensation Method 2 and between the auxiliary DPLL and

Compensation Method 3. The reason for the implied feedback

is that the indicated compensation destination (the auxiliary

DPLL, for example) can receive compensation from any of the

compensation sources via the combiner and distributor. Thus,

the compensation destination can potentially apply self

compensation, which leads to an undesired positive feedback

loop. The user must avoid such loops (see the Compensation

Assignment Guidelines section).

Each compensation method produces its own compensation

factors (CF1, CF2, and CF3). The combiner translates the three

CFx factors to eight possible combined compensation factors,

COMPx, according to Table 56. The index, x, of COMPx is the

3-bit value programmed in the associated compensation

destination bit field per Figure 104.

Table 56. Composite Compensation Factor (COMPx)

COMPx Index

(x)

Compensation Factor

Index

Combiner

Output

Not applicable

CF1

CF2

1, 2

CF1 × CF2

CF3

1, 3

CF1 × CF3

2, 3

CF2 × CF3

1, 2, 3

CF1 × CF2 × CF3

The distributor gives the user the ability to connect any COMPX

output from the combiner to any compensation destination.

The AD9545 implements the distributor through six 3-bit bit

fields, where each bit field corresponds to a specific

compensation destination per Figure 104. The user assigns a

COMPX factor to a particular destination by writing a 3-bit

value to the corresponding compensation destination bit field.

See the System Clock Compensation Programming Registers

section for a register programming example.

Note that any of the COMPx selections (except for COMP0)

constitute a real-time sequence of compensation values originating

from the various compensation sources. This real-time sequence

continuously applies to the associated compensation destination.

Because the COMPX outputs respond to the various stimuli

associated with the compensation sources, COMPx tends to

vary over time, causing the associated compensation destination

to vary accordingly. However, if the frequency variation vs. time

slope is too large, it can appear as an unwanted noise source to

compensation destinations employing closed-loop compensation

(such as DPLL0, DPLL1, and the auxiliary DPLL).

To mitigate the potential noise injection caused by COMPX

exhibiting an excessive frequency variation vs. time slope, the

combiner employs programmable rate limiting via a slew rate

limiter. The slew rate limiter effectively prevents the rate of

change of frequency originating with compensation sources

from exceeding a preset limit.

The user controls rate limiting via the 3-bit slew rate limit bit

field in Bits[D2:D0] of Register 0x0283 according to Table 57.

The rate limit values are in units of parts per million per second

(ppm/sec or 10−6/sec) and represent the maximum rate of

change of COMPX that occurs based on the slew rate limit bit

field value. Because rate limiting applies globally to COMP1

through COMP7, the user must base the rate limit selection on

the stability requirements of the most frequency sensitive

compensation destination.

COMPENSATION

METHOD 3

COMPENSATION

METHOD 2

COMPENSATION

METHOD 1

SLEW

RATE

LIMITER

CF3

CF2

CF1

COMP0

COMP7

COMP6

COMP5

COMP4

COMP3

COMP2

COMP1

DISTRIBUTOR

COMPENSATION

DESTINATIONS

COMPENSATION

METHODS

COMBINER

REFx TDCS AND

AUXILIARY TDCS

AUXILIARY DPLL

AUXILIARY NCO 0/NCO 1

DPLL 0/DPLL 1

Figure 103. Integrated Compensation Subsystem

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