AD9545 datasheet(130/157 Pages) AD

130 / 157 page

AD9545

Data Sheet

Rev. A | Page 130 of 157

COMPENSATION METHOD 2

Compensation Method 2 employs the closed-loop method of

system clock compensation (see the Closed-Loop Method section).

As shown in Figure 101, Compensation Method 2 makes use of one

of the DPLLx channels (where x is 0 or 1). The user must specify

which DPLL via the DPLL channel error source bit in Bit D0 of

DPLL1 as the source of CF2. CF2 embodies the factor, 1 + FFECOMP,

in Figure 98.

Compensation Method 2 generates the correction factor, CF2,

which the user can apply to other NCOs and TDCs within the

AD9545. However, a compensation factor, COMPx, can be applied

to the NCO of DPLLx in Figure 101. Because it is possible for the

COMPx factor to include CF2 (see the Integrated Compensation

Subsystem section for details), the user must ensure that the NCO

of the DPLL channel selected for Compensation Method 2 is not

itself a recipient of CF2 via COMPx.

XOA

XOB

SYSTEM

CLOCK

SOURCE

fSRC

AD9545

FTW

STABLE

FREQUENCY

SOURCE

FTW

ANALYZER

DPLLx

fREF

fNCO

CF2

FROM

FEEDBACK

TDC

REFERENCE

DIVIDER

AND TDC

COMPx

DIGITAL

PFD AND

LOOP

FILTER

NCO

SYSTEM

CLOCK PLL

Figure 101. Compensation Method Number 2

COMPENSATION METHOD 3

Compensation Method 3 employs the closed-loop method of

system clock compensation (see the Closed-Loop Method

section). As shown in Figure 102, Compensation Method 3

produces compensation factor CF3, where CF3 embodies the

factor, 1 + FFECOMP, in Figure 98. Compensation Method 3 is

similar to Compensation Method 2, but uses the auxiliary DPLL

rather than one of the DPLL channels. Because Compensation

Method 3 relies on the availability of a stable external clock

source applied to one of the REFx inputs or one of the Mx pins,

the user must assign the TDC associated with the external clock

source to the auxiliary DPLL via the 5-bit auxiliary DPLL

source bit field in Bits[D4:D0] of Register 0x0284. Table 55

shows the assignment codes for the various TDCs.

The auxiliary DPLL can itself receive compensation from other

sources via COMPx in Figure 102 (see the Integrated

Compensation Subsystem section for details). Unlike

Compensation Method 2, the CF3 compensation factor does not

include the contribution of COMPx. That is, CF3 comprises only

the residual error to represent the frequency deviation

associated with the system clock source only.

Table 55. Auxiliary DPLL TDC Assignment Codes

Auxiliary DPLL Source Bit Field

5-Bit Code

TDC Description

00000

REFA TDC (default)

00001

REFAA TDC

00010

REFB TDC

00011

REFB TDC

00100

Unused

00101

Unused

00110

Auxiliary TDC 0

00111

Auxiliary TDC 1

01000 to 11111

Unused

Assuming the auxiliary DPLL is locked and has fully settled, the

period of the stable reference must exactly match the period

indicated by the contents of the appropriate REFx nominal

period (see Register 0x0404 to Register 0x040B, Register 0x0424

to Register 0x042B, Register 0x0444 to Register 0x044B,

fields (see Register 0x2A01 to Register 0x2A08 and Register

0x2A0A to Register 0x2A11). Any deviation is an indication of

error associated with the system clock period and leads to a

corresponding CF3 value. There are two error sources: stability

error and accuracy error.

Stability error involves deviation from the mean value over time

(the mean corresponding to a specific operating condition like

25°C, for example). Consider what happens as temperature

varies over time. The frequency of the oscillator serving as the

source for the system clock varies in response to the

temperature changes. Given the prerequisite that the stable

reference is significantly more stable than the system clock

source, the dominant variations appearing in the feedback path

are those of the system clock. Because the system clock

variations are the dominant contributor to CF3, CF3 reflects the

corrections necessary to compensate for the temperature-

induced stability errors on the system clock.

Accuracy error is the difference between the desired nominal

frequency and the actual frequency. The desired nominal

frequency derives from the entry of the user in the REFx

nominal period or Auxiliary x period bit fields. The actual

frequency is fREF, the true frequency of the stable reference (see

Figure 102). The accuracy error is the difference between the

user entry and the actual nominal period of the stable reference.

Because CF3 is a composite of both the stability and accuracy

error sources, the reference period entry of the user via the

REFx nominal period or Auxiliary x period bit fields directly

effects the accuracy error component of CF3. Thus, accurate

entry of the stable reference clock period is crucial, because the

accuracy error propagates to any COMPx involving CF3 (see the

Integrated Compensation Subsystem section).

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