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AD9545

Data Sheet

Rev. A | Page 126 of 157

Note that the term, (1 + FFE) × (1 − FFE), simplifies to 1 −

FFE2. Given that FFE2 = FFECOMP × FFE, if both FFECOMP and

FFE are less than 1 ppm (10−6), a reasonable assumption, then

FFE2 is less than 10−12 (one part in a trillion). For FFE values

below 1 ppm, the value of FFE2 is exceedingly small. Under such

conditions, FFE2 is practically zero, and Equation 23 simplifies

to the following:

fNCO

= f0 × KPLL × FTW × KNCO

This expression for fNCO is the same as fNCO_IDEAL. Therefore, the

FFE associated with the system clock source is nullified by

applying the fractional correction term, FFECOMP.

The preceding example demonstrates the viability of

compensating for the system clock FFE. However, FFE

compensation is of little value without a means of predicting

FFE so that the appropriate correction can be applied. In this

regard, the open-loop method relies on two assumptions.

•

Temperature variation dominates the FFE of the system

clock source

•

The FFE vs. temperature (T) behavior of the system clock

source takes the form of an x-order polynomial

In the case of the AD9545, x = 5; therefore, the latter

assumptions is expressible as

FFESRC

= c5T5 + c4T4 + c3T3 + c2T2 + c1T1 + c0

(24)

where the coefficients, cx, define the shape of the FFESRC curve.

c0 constitutes a static offset, whereas the remaining coefficients

relate to powers of T. Note also, that any particular power of T

can be artificially eliminated by assigning its corresponding

coefficient to zero. For example, reduce the polynomial to

second order by making the c5, c4, and c3 coefficients in

Equation 24 equal to zero. The open-loop method assumes

advance knowledge of the cx values, which the user programs

into the appropriate AD9545 register map locations.

The overall concept of the open-loop method is to program the

AD9545 with the appropriate coefficients, cx, such that the

polynomial closely models the temperature dependent behavior

of the system clock source. The AD9545 has a builtin

compensation calculator to implement the FFE polynomial (see

the Compensation Method 1 section for more details). The

AD9545 provides the means to apply the correction factor

generated by the compensation calculator to the NCOs and

TDCs designated by the user.

Closed-Loop Method

The closed-loop method, unlike the open-loop method,

requires no advance knowledge of the FFE behavior of the

system clock source. Instead, it relies on a DPLL and the

availability of a very stable external frequency source (GPS, for

example) as a reference input to the DPLL (see Figure 98).

In operation, assuming the DPLL is locked and stable, the FTW

applied to the NCO is relatively constant. Especially under the

assumption that the frequency of the stable frequency source is

constant and the frequency of the system clock source is

constant. However, the frequency of the stable frequency source

is constant, by definition, a necessary condition of the closed-

loop method. As such, fNCO is constant because the feedback

loop of the DPLL ensures fNCO = N × fREF. Therefore, should fSRC

change (due to temperature, for example), the DPLL feedback

loop causes FTW to change in a manner that maintains a

constant fNCO. Because the FFE of the stable source is zero (it is

error free, presumably), then any FFE associated with fNCO must

be attributable to the FFE of the system clock source.

That is, the FFE of the system clock source translates

deterministically to a deviation of FTW (from its nominal

value, FTW0).

In the closed-loop method, FTW variations lead to a correction

factor, 1 + FFECOMP. The FTW analyzer shown in Figure 98 is an

integral component of the AD9545. Applying the correction

factor to other designated NCOs and TDCs in the AD9545 is

the basis of the closed-loop method.

FTW

OTHER NCO OR TDC

CORRECTED

FTW

1 + FFECOMP

XOA

XOB

fSRC

AD9545

SYSTEM

CLOCK PLL

SYSTEM

CLOCK

SOURCE

DPLL

fREF

STABLE

FREQUENCY

SOURCE

FTW

ANALYZER

1 + FFECOMP

NCO

DIGITAL

PHASE

DETECTOR

DIGITAL

LOOP

FILTER

÷N

fNCO

Figure 98. Closed-Loop Method

The dynamic and automatic compensation capability of the

closed-loop method typically offers improved performance over

the open-loop method but requires the availability of a stable

frequency source. In general, the stable frequency source must

be at least 10 times more stable than the system clock source for

the closed-loop method to be viable.

The AD9545 employs two forms of the closed-loop method.

The first form uses one of the DPLL channels (DPLL0 or

DPLL1) as the DPLL shown in Figure 98. The second form uses

an independent special purpose DPLL (the auxiliary DPLL) as

the DPLL shown in Figure 98. The latter form allows the user to

implement closed-loop system clock compensation without

sacrificing one of the DPLL channels.

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