AD9545 datasheet(134/157 Pages) AD

134 / 157 page

AD9545

Data Sheet

Rev. A | Page 134 of 157

STATUS AND CONTROL PINS

STATUS AND CONTROL PINS OVERVIEW

The AD9545 features seven independently configurable digital

CMOS status/control pins (M0 to M6). Configuring an Mx pin

as a status pin causes that pin to be an output. Conversely,

configuring an Mx pin as a control pin causes that pin to be an

input. Register 0x0102 to Register 0x0108 control both the

nature of the pin (either status or control via Bit D7), as well as

the selection of the status source or control destination

associated with the pin via Bits[D6:D0]. During power-up or

reset, the Mx pins temporarily become inputs and only allow the

device to autoconfigure. Figure 105 is a block diagram of the Mx

pin functionality.

CONTROL

FUNCTION

SELECT

STATUS

SOURCE

SELECT

Mx PIN

CONTROL

REGISTERS

I/O_UPDATE

I/O

CONTROL

DEVICE

RESET

POWER UP

AUTOCONFIGURATION

CONTROL

DESTINATIONS

STATUS

SOURCES

Mx PIN FUNCTION LOGIC

Figure 105. Mx Pin Logic

The Mx pin control logic uses special register write detection

logic to prevent these pins from behaving unpredictably when the

Mx pin function changes, especially when changing mode from

input to output or vice versa.

When an Mx pin functions as an output, it continues operating

according to the prior function, even after the user programs

the corresponding registers. However, assertion of an input/output

update causes the corresponding pins to switch to the new

function according to the newly programmed register contents.

Note that changing from one output function to another output

function on an Mx pin does not require special timing to avoid

input/output contention on the pin.

When an Mx pin functions as an input, programming a particular

Mx pin function register causes all the Mx pin control functions

to latch their values. Assertion of an input/output update

switches to the newly programmed pin function, at which time

normal behavior resumes. Note that, when switching from one

input function to another input function on the same pin, the

logic state driven at the input to the pin can change freely

during the interval between writing the new function to the

corresponding register and asserting the input/output update.

When switching the operation of an Mx pin from an input to an

output function, the recommendation is that the external drive

source become high impedance during the interval between

writing the new function and asserting the input/output update.

When switching the operation of an Mx pin from an output to

an input, the recommendation is as follows. First, program the

Mx pin input function to no operation (NOOP) and assert the

input/output update. This configuration avoids input/output

contention on the Mx pin or other undesired behavior because,

prior to the assertion of the input/output update, the device

continues to drive the Mx pin. Following the assertion of the

input/output update, the device releases the Mx pin but ignores

the logic level on the pin due to the programmed NOOP function.

The recommendation is to avoid using a high impedance source on

an Mx pin configured as an input because this may cause

excessive internal current consumption. Second, drive the Mx

pin with Logic 0 or Logic 1 via the desired external source and

program the associated Mx pin register from NOOP to the

desired function.

MULTIFUNCTION PINS AT RESET/POWER-UP

At power-up or in response to a reset operation, the Mx pins

enter a special operating mode. For a brief interval following a

power-up or reset operation, the Mx pins function only as

inputs (the internal drivers enter a high impedance state during

a power-up/reset operation). During this brief interval, the

device latches the logic levels at the Mx inputs and uses this

information to autoconfigure the device accordingly. The Mx

pins remain high-Z until either an EEPROM operation occurs,

in which case M1 or M2 become an I2C master, or the user (or

EEPROM) programs them to be outputs.

If the user does not connect external pull-up/pull-down resistors

to the Mx pins, the M3 and M4 pins have internal pull-down

resistors to ensure a predictable start-up configuration. In the

absence of external resistors, the internal pull-down resistors

ensure that the device starts up with the serial port in SPI mode

and without automatically loading data from an external EEPROM

(see Table 58). Although the M0, M1, M2, M5, and M6 pins are

high impedance at startup, connect external 100 kΩ pull-down

or pull-up resistors to these pins to ensure a deterministic start-up

condition.

Table 58 shows the Mx pin start-up conditions. M0, M1, and

M2 do not appear in Table 58 because these pins have no

explicit function during a power-up or reset operation.

Table 58. Mx Pin Function at Startup or Reset

Startup/Reset

Function

Logic 1

Logic 0

EEPROM load

function

Load from

EEPROM

Do not load from

EEPROM (default)

Serial port function

I²C mode

SPI mode (default)

I2C address offset

See Table 59

I2C address offset

See Table 59

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