8101 datasheet(142/172 Pages) LSI

142 / 172 page

5-16

Application Information

5.8 TX Packet and Octet Counters

The controller counter set includes packet and octet counters for the

transmit and receive packets. The RMON speciﬁcations state that packet

and octet counters should only tabulate received information. This is

sometimes interpreted to mean both transmitted and received

information, because Ethernet was originally a shared media protocol. As

such, the tables above only point to receive packet and octet counters,

but the transmit packet and octet counters are also available in counters

17 through 26 and can be summed with the receive packet and octet

counts if desired.

5.9 Power Supply Decoupling

There are 23 VCCs (VCC[22:0]) and 31 GNDs (GND[30:0]) on the

controller. All GNDs should also be connected to a large ground plane.

If the GNDs vary in potential by even a small amount, noise and latch up

can result. The GNDs should be kept to within 50 mV of each other.

Some of the VCC pins on the controller go to the internal core logic, and

the remaining VCCs go to the I/O buffers. The core and I/O VCCs should

be isolated from each other to minimize jitter on the 10-bit PHY interface.

It is recommended that all of the I/O VCCs be directly connected to a

large VCC plane. It is also recommended that the core VCCs (pins 70,

aUnsupportedOpcodesReceived

0b11100100

0b11100101

aPauseMACCtrlFramesTransmitted

0b11100110

0b11100111

aPauseMACCtrlFramesReceived

0b11101000

0b11101001

Table 5.8

MIB Objects vs. Counter Location For Ethernet MIB

(IEEE 802.3z, Clause 30) (Cont.)

Counter Location

MIB Objects

Counter

(Low/High)

8101 Datasheet(PDF) 142 Page - LSI Computer Systems