8101 datasheet(144/172 Pages) LSI

144 / 172 page

5-18

Application Information

and digital VCC pins on the SerDes device should be isolated from each

other with a ferrite bead placed between the analog SerDes VCC pins

and the digital SerDes VCC pins, as shown in Figure 5.2. Decoupling

capacitors should then be placed between the SerDes device VCC pins

and GND plane, as shown in Figure 5.2 and described as follows.

For the controller and other digital devices there should be a pair of

0.1

µf and 0.001 µf decoupling capacitors connected between VCC and

GND for every four sets of VCC/GND pins placed as close as possible

to the device pins, preferably within 0.5" and evenly distributed around all

four sides of the devices. For the external SerDes device, there should

be a pair of 0.1/0.001

µf capacitors for every two sets of VCC/GND pins.

The 0.1

µf and 0.001 µf capacitors reduce the LOW and HIGH frequency

noise, respectively, on the VCC at the device.

The PCB layout and power supply decoupling discussed above should

provide sufﬁcient decoupling to achieve the following when measured at

the device:

• The resultant AC noise voltage measured across each VCC/GND set

should be less than 100 mVpp.

• All VCCs should be within 50 mVpp of each other.

• All GNDs should be within 50 mVpp of each other.

8101 Datasheet(PDF) 144 Page - LSI Computer Systems