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8101 Datasheet(PDF) 154 Page - LSI Computer Systems |
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8101 Datasheet(HTML) 154 Page - LSI Computer Systems |
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154 / 172 page  6-10 Specifications Copyright © 2000–2001 by LSI Logic Corporation. All rights reserved. Note: Refer to Figure 6.6 for timing diagram. Figure 6.6 System Interface RXDC/TXDC Timing Table 6.5 System Interface RXDC/TXDC Timing Characteristics Symbol Parameter Limit Unit Conditions Min Typ Max t51 TXDC/RXDC assert delay time 08 ns t52 TXDC/RXDC deassert delay time 0 2 SCLK cycle +8ns ns AutoClear mode off 0 3 SCLK cycle +8ns ns AutoClear mode on t53 CLR_TXDC/RXDC setup time 5ns t54 CLR_TXDC/RXDC hold time 0ns TXDC/RXDC rise and fall time 4ns SCLK TXENn CLR_TXDC TXEOF RXEOF t53 TXDC t51 t52 t54 RXENn RXDC CLR_RXDC Autoclear Mode Off Autoclear Mode Off |
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