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8101 Datasheet(PDF) 157 Page - LSI Computer Systems |
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8101 Datasheet(HTML) 157 Page - LSI Computer Systems |
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157 / 172 page  AC Electrical Characteristics 6-13 Copyright © 2000–2001 by LSI Logic Corporation. All rights reserved. Note: Refer to Figure 6.9 and Figure 6.10 for timing diagrams. Table 6.8 Register Interface Timing Characteristics Symbol Parameter Limit Unit Conditions Min Typ Max t81 REGCSn, REGWRn, REGRDn, REGA, REGD setup time 10 ns t82 REGCSn, REGWRn, REGRDn, REGA, REGD hold time 1ns t83 REGCLK to REGD active delay 10 ns Read cycle. All registers except Counter Registers 1–53 6 REGCLK cycles + 10 ns ns Read cycle. Counter Registers 1–53, first 16 bits of counter result 3 REGCLK cycles + 10 ns ns Read cycle. Counter Registers 1–53, second 16 bits of counter result t84 REGCLK to REGD 3-state delay 010 ns t85 REGCLK to REGINT assert delay 020 ns t86 REGCLK to REGINT deassert delay 020 ns t87 Deassertion time between reads 4 REG- CLK |
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