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8101 Datasheet(PDF) 156 Page - LSI Computer Systems |
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8101 Datasheet(HTML) 156 Page - LSI Computer Systems |
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156 / 172 page ![]() 6-12 Specifications Copyright © 2000–2001 by LSI Logic Corporation. All rights reserved. Note: Refer to Figure 6.8 for timing diagram. Figure 6.8 Receive 10-Bit PHY Interface Timing Table 6.7 Receive 10-Bit PHY Interface Timing Characteristics Symbol Parameter Limit Unit Conditions Min Typ Max t71 RBC frequency 62.4937 62.5 62.5063 MHz t72 RBC HIGH time 6.4 9.6 ns 6.4 128 ns During synchronization t73 RBC LOW time 6.4 9.6 ns 6.4 128 ns During synchronization t74 RBC skew 7.5 8.5 ns t75 RX[0:9] setup time 2.5 ns t76 RX[0:9] hold time 1.5 ns t77 RBC, RX[0:9] rise and fall time 0.7 2.4 ns t76 t75 t77 RBC1 RX[0:9] t74 t77 t77 t77 t71 t76 t75 t72 t73 t72 t73 t71 t77 RBC0 |
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