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8101 Datasheet(PDF) 155 Page - LSI Computer Systems |
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8101 Datasheet(HTML) 155 Page - LSI Computer Systems |
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155 / 172 page ![]() AC Electrical Characteristics 6-11 Copyright © 2000–2001 by LSI Logic Corporation. All rights reserved. Note: Refer to Figure 6.7 for timing diagram. Figure 6.7 Transmit 10-Bit PHY Interface Timing Table 6.6 Transmit 10-Bit PHY Interface Timing Characteristics Symbol Parameter Limit Unit Conditions Min Typ Max t61 TBC period 7.992 8 8.008 ns t62 TBC HIGH time 3.2 4.8 ns t63 TBC LOW time 3.2 4.8 ns t64 TX[0:9] data valid before TBC rising edge 2.0 ns Assumes TBC duty cycle = 40 −60% t65 TX[0:9] data valid after TBC rising edge 1.0 ns Assumes TBC duty cycle = 40–60% t66 TBC, TX[0:9] rise and fall time 0.7 2.4 ns t66 TBC TX[0:9] t62 t63 t61 t64 t65 t66 t66 |
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