TC35680FSG datasheet(36/91 Pages) TOSHIBA

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TC35680FSG-002/TC35681FSG-002

2019-04-04

4.5. Reset Interface

Feature

The reset interface has the following features;



Reference I/O power supply: VDDIO



Level sensitive asynchronous reset (Low level is active.)

After the power is supplied, the external reset signal should be deasserted (RESETX pin = High) when the VBAT reaches the

minimum value of the VBATopr shown in Section 5.2 and the VDDIO reaches the minimum value of the VDDIOopr. After the external

reset is deasserted, the crystal resonator of the reference clock starts oscillation. The internal reset is deasserted after the time interval

for the oscillation of a crystal resonator stability elapses (a built-in timer measures the interval).

The reset signal, RESETX should be asserted (Low level) for

1 μs or more.

Connection Example

The reset signal can be generated by an RC time constant circuit or can be supplied by the device which generates a level sensitive

asynchronous reset signal. The RC time constant circuit can generate a delay signal for the start-up of the power supply.

“Reset in the User-App mode” in Figure 4-1 shows an example of this connection.

And “Reset by Host CPU” in Figure 4-1 shows an example of the connection of the device which generates a level sensitive

asynchronous reset signal. When a JTAG emulator is connected, the reset pin of the host CPU is connected to the reset pin of the

JTAG emulator using a wired-OR connection. The reset of this device is asserted by the low level output of either the host CPU or

the JTAG emulator.

Figure 4-1 Example of Reset signal connection

TC35680/

TC35681

Reset

Power supply

Note: The circuits in the diagram of connection example are simplified and omit details.

■ Reset in User-App mode

■

Reset by Host CPU

TC35680/

TC35681

Reset

Host CPU

VDDIO

JTAG emulator

Wired-OR

RC time constant circuit

TC35680FSG Datasheet(PDF) 36 Page - Toshiba Semiconductor