TC35680FSG datasheet(61/91 Pages) TOSHIBA

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TC35680FSG-002/TC35681FSG-002

2019-04-04

4.12. Reference Clock Interface

Feature

The reference clock interface has the following features;



Reference clock frequency: 32 MHz



Clock frequency accuracy: ±50 ppm or less is necessary. (in operating environment)



Built-in 128-step variable capacitor (1.24 to 20.4 pF)



Load capacitance and equivalent series resistance of the crystal resonator



Load capacitance: 6 pF



Equal series resistance: 50

Ω (recommended)

An external feedback resistor and external capacitors are unnecessary for the crystal oscillation circuit in TC35680/TC35681,

because the devices integrate the feedback resistor and a variable capacitor (1.24 to 20.4 pF) on the input and output pins of the

crystal resonator. A crystal resonator which has a load capacitance of 6 pF should be connected between the XOIN and XOOUT

pins, and the capacitance of the variable capacitor should be adjusted so that the frequency deviation does not exceed ±50 ppm

under the use environment.

The recommended equivalent series resistance of the crystal resonator is 50

Ω. The oscillation margin should be evaluated

sufficiently when a crystal resonator with a larger equivalent series resistance is used. And the interval time for the oscillation stability

should be 1.5 ms or less.

Adjustment of Oscillation Frequency of Reference Clock

The adjustment of the oscillation frequency is done by the modification of the capacitance of the variable capacitor. It is done by the

setting of the 7-bit XO_FREQ_TUNE field in the PMU_XOSC_TRIMIN register. When a value between 0x00 and 0x7F (2’s

complement) is set, the capacitance of the variable capacitors on the input and output pins changes with a step of approximately

0.15 pF. Then, the value 0x40 gives the minimum frequency and 0x3F, the maximum frequency.

The value of XO_FREQ_TUNE is 0x00 just after the hardware reset is deasserted or while the cold boot is done. It is set to 0x1A by

the built-in firmware after the oscillation becomes stable. Then the value can be modified by a software procedure.

For the details of the adjustment of the variable capacitor, refer to the “Hardware Application Note”.

Low Power Mode and Adjustment Value

The oscillation stops in a low power mode. When the wake-up is done in the Sleep mode or the Backup mode, the oscillation start

is controlled by the value in the XO_FREQ_TUNE field which is set before the transition to the low power mode. So the value is

different from the value in the XO_FREQ_TUNE field in the cold boot procedure. Then the interval time for oscillation stability is also

different. The time should not exceed 1.5 ms.

Table 4-14 shows the oscillation condition and the value in the XO_FREQ_TUNE field.

Table 4-14 Oscillation condition of the reference clock and XO_FREQ_TUNE value

Oscillation condition

Value in XO_FREQ_TUNE

Just after hardware reset is deasserted or wake-up from

the Deep Sleep mode.

0x00 (the initial value at start-up)

0x1A (the initial value after the oscillation

becomes stable)

Wake-up from the Sleep or Backup mode

User setting value (Initial value is 0x1A)

TC35680FSG Datasheet(PDF) 61 Page - Toshiba Semiconductor

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