TC35680FSG datasheet(44/91 Pages) TOSHIBA

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TC35680FSG-002/TC35681FSG-002

2019-04-04

Frame Format

TC35680/TC35681 support the following formats;

 Data bit length: 8 bits (LSB first)

 Parity bit:

No parity, odd, or even

 Stop bit length: 1 bit or 2 bits

 Flow control:

RTSX and CTSX (optional)

An example of the UART data frame is shown in Figure 4-5.

Figure 4-5 Data frame

Flow Control Function

The hardware flow control is available when the GPIOs of TC35680/TC35681 are assigned to the UART interface of the 4-wire. The

signal directions are shown in Figure 4-6.

The flow control can be used to prevent from the overflow of the data buffers.

Figure 4-6 Example of UART connection

When the CTSX (Clear to Send) input signal is High, TC35680/TC35681 complete the transmission of a current frame of data and

then stops. When the CTSX input is Low, the devices start to transmit data. If no transmission data is present, the transmission is not

done.

When the RTSX (Request to Send) output signal is High, it requests the host CPU to stop the data transmission.

When the RTSX output is Low, the data transmission from the host CPU is permitted.

The response time of the UART data transmission and reception to the flow control signals is the interval between 1-frame time

(minimum) and 4-frame time (maximum). It depends on the baud rate and the internal procedure status of the frame.

LSB

MSB

Start bit

Stop bit

LSB

MSB

Start bit

Stop bit

Over-sampling: (× n)/bit

UART transmission

data: TX

UART transmission

flow control: CTSX

UART reception data:

UART reception flow

control: RTSX

TC35680/

TC35681

UART reception flow control (RTSX)

UART transmission flow control (CTSX)

UART reception data (RX)

UART transmission data (TX)

HOST CPU

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