TC35680FSG datasheet(57/91 Pages) TOSHIBA

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TC35680FSG-002/TC35681FSG-002

2019-04-04

4.10. PWM Interface

Feature

The PWM interface has the following features;



Reference I/O power supply: VDDIO



Pulse generation function



Channel number: 4 for QFN package



The clock source to generate pulses can be selected between a 16-MHz clock (2-division of the reference clock) and

a 32.768-kHz clock.



The following output frequencies can be selected using a clock divider.



8 Hz to 16.384 kHz (the 32.768-kHz clock is used. 12-bit divider: the maximum division is 1/4096.)



0.954 Hz to 8 MHz (the 16-MHz clock is used. 12-bit × 2 divider: the maximum division is 1/16777216)



A pulse output can be masked with a 50-ms unit width (as example) by a regular pattern signal whose period is one

second (Rhythm function).



An interrupt can be generated every 1 second of the rhythm pattern period.



The pulse can be reversed.



The duty ratio of the pulse output can be adjusted.



Each PWM output can be synchronized by the pulse output synchronization function.

TC35680/TC35681 have a PWM interface that can be used for the LED control, the buzzer control, and others.

The PWM interface operates at the VDDIO power supply voltage. Because the power supply pin is shared with other hardware

interfaces, the voltage of the PWM interface cannot be independently different.

Pulse Generation Function

Figure 4-17 shows a PWM pulse waveform.

The frequency of the pulse signal is adjusted by changing the cycle time. The ON/OFF ratio can be adjusted by changing the duty

ratio.

The frequency can be set to the value from 8 Hz to 16.384 kHz (in use of the 32.768-kHz clock), and from 0.954 Hz to 8 MHz (in use

of the 16-MHz clock).

The duty ratio can be set to the value from 0 % to 100 %.

Figure 4-17 PWM pulse waveform

Cycle time

Duty ratio

TC35680FSG Datasheet(PDF) 57 Page - Toshiba Semiconductor

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