TC35680FSG datasheet(47/91 Pages) TOSHIBA

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TC35680FSG-002/TC35681FSG-002

2019-04-04

Error Detection Function

The UART interface in TC35680/TC35681 can detect 3 following errors;



Reception timeout error



Reception overrun error



Reception framing error

4.7.7.1. Reception Timeout Error

The availability of the timeout setting depends on an operating mode and a setting target interface. Table 4-8 shows the availability

of the timeout setting.

When the reception timeout is enabled, no data reception notifies the timeout error. The setting can be disabled.

Table 4-8 Availability of the timeout setting and the initial value

Operating mode

HCI mode

Complete mode

User-App mode

Setting method

HCI command

API

Setting target

Only UART1

Only UART1 (Note 2)

UART1 and UART2

Initial timeout setting

Disabled.

Enabled

Disabled

Initial timeout value

5 ms (Note 1)

1.04 ms

User setting value

Initial vale of register

Reception

Configurable

Note 1: The error occurs when the value exceeds 5 ms.

Note 2: Only UART1 can be set by the API in the User-App mode. When UART2 is used, the setting should be done by the register.

4.7.7.2. Reception Overrun Error

The reception overrun error occurs when the UART reception frame buffer in TC35680/TC35681 overflows. Normally, this overflow

error does not occur when the flow control described in Section 4.7.4 is used for data transfer.

4.7.7.3. Reception Framing Error

The reception framing error occurs when “0” is detected at the stop bit.

TC35680FSG Datasheet(PDF) 47 Page - Toshiba Semiconductor

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