C200 datasheet(57/82 Pages) INTEL

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Specification Update

Documentation Changes

h. SUSPWRDNACK is mobile only - this is more clearly indicated in table 2-8 and table

8-9.

i. ACPRESENT is mobile only - this is more clearly indicated in table 2-8 and sections

5.13.7.6.1 and 5.13.7.6.2.

j. HDA_DOCK_EN# and HDA_DOCK_RST# pin functionality are mobile only - this is

more clearly indicated in table 2-14.

k. Section 13.10.2—GP_IO_SEL register default value is changed to EEFF66EFFh.

l. Section 13.10.15—GP_IO_SEL3 register default value is changed to 00000FF0h.

m. “Intel® RST SSD Caching” is changed to “Intel® Smart Response Technology” and

note 11 is removed from table 1-2.

n. The register named GPIO_SEL3 (GPIOBASE +44h) is changed to GP_IO_SEL3.

16.

Ballout Documentation Changes

a. In table 6-1, the following changes are made:

• Remove BATLOW# from GPIO72

• Remove HDA_DOCK_RST# from GPIO13

• Remove HDA_DOCK_EN# from GPIO33

• Remove CLKRUN# from GPIO32

• Remove SUSPWRDNACK from SUSWARN# / GPIO30 (and add spaces)

17.

Integrated Digital Display Audio Device and Revision IDs

a. The title of section 17.2 is changed to Integrated Digital Display Audio Registers,

Verb IDs, and Device/Revision IDs

b. The following section is added at the conclusion of section 17.2.1:

Integrated Digital Display Audio Device ID and Revision ID

The Intel 6 Series Chipset/Intel C200 Series Chipset provides a Device ID of 2805h for

the integrated digital display audio codec. This is not a PCI Device ID. Instead, it is a

Device ID associated with the Intel HD Audio bus.

The integrated digital display codec Revision ID is 00h for all PCH steppings.

Memory Range

Target

Dependency/Comments

FEC1 8000h–FEC1 FFFFh

PCI Express* Port 2

PCI Express* Root Port 2 I/OxAPIC Enable (PAE) set

FEC2 8000h–FEC2 FFFFh

PCI Express* Port 4

PCI Express* Root Port 4 I/OxAPIC Enable (PAE) set

FEC3 8000h–FEC3 FFFFh

PCI Express* Port 6

PCI Express* Root Port 6 I/OxAPIC Enable (PAE) set

C200 Datasheet(PDF) 57 Page - Intel Corporation

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