C200 datasheet(59/82 Pages) INTEL

59 / 82 page

Specification Update

Documentation Changes

e. Section 21.4.4 FADDR—Flash Address Register (GbE LAN Memory Mapped

Configuration Registers) bits 24:0 are modified as shown:

f. Section 21.4.6 FRAP—Flash Regions Access Permissions Register (GbE LAN Memory

Mapped Configuration Registers) is modified as shown:

g. Bits 7 and 6 of section 21.4.13 SSFS—Software Sequencing Flash Status Register

(GbE LAN Memory Mapped Configuration Registers) are added as:

Bit

Description

Access Error Log (AEL)— R/WC. Hardware sets this bit to a 1 when an attempt was

made to access the GbE region using the direct access method or an access to the GbE

Program Registers that violated the security restrictions. This bit is simply a log of an

access security violation. This bit is cleared by software writing a 1.

Bit

Description

24:0

Flash Linear Address (FLA) — R/W. The FLA is the starting byte linear address of a

SPI Read or Write cycle or an address within a Block for the Block Erase command. The

Flash Linear Address must fall within a region for which GbE has access permissions.

Bit

Description

31:24

GbE Master Write Access Grant (GMWAG) — R/W. Each bit 31:24 corresponds to

Master[7:0]. GbE can grant one or more masters write access to the GbE region 3

overriding the permissions in the Flash Descriptor.

Master[1] is Host Processor/BIOS, Master[2] is Intel® Management Engine, Master[3]

is Host processor/GbE. Master[0] and Master[7:4] are reserved.

The contents of this register are locked by the FLOCKDN bit.

23:16

GbE Master Read Access Grant (GMRAG) — R/W. Each bit 23:16 corresponds to

Master[7:0]. GbE can grant one or more masters read access to the GbE region 3

overriding the read permissions in the Flash Descriptor.

Master[1] is Host processor/BIOS, Master[2] is Intel® Management Engine, Master[3]

is GbE. Master[0] and Master[7:4] are reserved.

The contents of this register are locked by the FLOCKDN bit

15:8

GbE Region Write Access (GRWA) — RO. Each bit 15:8 corresponds to Regions 7:0.

If the bit is set, this master can erase and write that particular region through register

accesses.

The contents of this register are that of the Flash Descriptor. Flash Master 3. Master

Region Write Access OR a particular master has granted GbE write permissions in their

Master Write Access Grant register OR the Flash Descriptor Security Override strap is

set.

7:0

GbE Region Read Access (GRRA) — RO. Each bit 7:0 corresponds to Regions 7:0. If

the bit is set, this master can read that particular region through register accesses.

The contents of this register are that of the Flash Descriptor. Flash Master 3. Master

Region Write Access OR a particular master has granted GbE read permissions in their

Master Read Access Grant register.

Bit

Description

Fast Read Supported — RO. This bit reflects the value of the Fast Read Support bit in

the flash Descriptor Component Section.

Dual Output Fast Read Supported — RO. This bit reflects the value of the Dual

Output Fast Read support bit in the Flash Descriptor Component Section

C200 Datasheet(PDF) 59 Page - Intel Corporation

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