C200 datasheet(79/82 Pages) INTEL

79 / 82 page

Specification Update

Documentation Changes

The Device Driver code should do the following for an available timer:

1. Set the Overall Enable bit (Offset 10h, bit 0).

2. Set the timer type field (selects one-shot or periodic).

3. Set the interrupt enable.

4. Set the comparator value.

5.17.5 Interrupt Levels

Interrupts directed to the internal 8259s are active high. See Section 5.9 for

information regarding the polarity programming of the I/O APIC for detecting internal

interrupts.

If the interrupts are mapped to the 8259 or I/O APIC and set for level-triggered mode,

they can be shared with PCI interrupts.

If more than one timer is configured to share the same IRQ (using the

TIMERn_INT_ROUT_CNF fields), then the software must configure the timers to

level-triggered mode. Edge-triggered interrupts cannot be shared.

5.17.6 Handling Interrupts

Section 2.4.6 of the IA-PC HPET Specification describes Handling Interrupts.

5.17.7 Issues Related to 64-Bit Timers with 32-Bit Processors

Section 2.4.7 of the IA-PC HPET Specification describes Issues Related to 64-Bit Timers

with 32-Bit Processors.

b. The following replaces section 5.27.5:

5.27.5 Virtualization Support for High Precision Event Timer (HPET)

The Intel VT-d architecture extension requires Interrupt Messages to go through the

similar Address Remapping as any other memory requests. This is to allow domain

isolation for interrupts such that a device assigned in one domain is not allowed to

generate interrupts to another domain.

The Address Remapping for Intel VT-d is based on the Bus:Device:Function field

associated with the requests. Hence, it is required for the HPET to initiate processor

message interrupts using unique Bus:Device:Function.

The PCH supports BIOS programmable unique Bus:Device:Function for each of the

HPET timers. The Bus:Device:Function field does not change the HPET functionality in

anyway, nor promoting it as a stand-alone PCI device. The field is only used by the

HPET timer in the following:

• As the Requestor ID when initiating processor message interrupts to the processor

• As the Completer ID when responding to the reads targeting its Memory-Mapped

registers

• The registers for the programmable Bus:Device:Function for HPET timer 7:0 reside

under the Device 31:Function 0 LPC Bridge’s configuration space.

C200 Datasheet(PDF) 79 Page - Intel Corporation