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C200 Datasheet(PDF) 20 Page - Intel Corporation |
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C200 Datasheet(HTML) 20 Page - Intel Corporation |
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20 / 82 page ![]() Errata 20 Specification Update 11. SATA Differential Return Loss Violations Problem: The Intel 6 Series Chipset and Intel C200 Series Chipset SATA buffer capacitance may be higher than expected. Implication: There are no known functional failures. This may cause a violation of the SATA-IO* compliance test for Receiver or Transmitter Differential Return Loss. Workaround: None. Note: Intel has obtained a waiver for the SATA-IO building block status. Status: No Plan to Fix. 12. High-speed USB 2.0 Transmit Signal Amplitude Problem: Intel 6 Series Chipset and Intel C200 Series Chipset High-speed USB 2.0 transmit signal amplitude may exceed the USB 2.0 specification. • USB 2.0 Specification Transmit Eye template maximum boundary is +/- 525 mV following bit transitions and +/- 475 mV for non-transitional bit patterns. • USB 2.0 Specification VHSOH maximum is 440 mV. Implication: There are no known functional failures. Workaround: None. Status: No Plan to Fix. 13. Delayed Periodic Traffic Timeout Issue Problem: If a periodic interrupt transaction is pushed out to the x+4 microframe boundary, the RMH may not wait for the transaction to timeout before starting the next transaction. Implication: If the next full-speed or low-speed transaction is intended for the same device targeted by the periodic interrupt, the successful completion of that transaction is device dependent and cannot be guaranteed. The implication may differ depending on the nature of the transaction: • If the transaction is asynchronous and the device does not respond, it will eventually be retried with no impact. • If the transaction is periodic and the device does not respond, the transfer may be dropped. A single dropped periodic transaction should not be noticeable by end user. Note: This issue has only been seen in a synthetic environment. Workaround: None. Status: No Plan to Fix. |
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