C200 datasheet(52/82 Pages) INTEL

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Documentation Changes

Specification Update

g. 82C37 is changed to 8237 throughout document.

h. 82C54 is changed to 8254 throughout document.

i. 82C59 is changed to 8259 throughout document.

j. The second paragraph of section 5.10 is changed as shown:

The PCH supports a message for 21 serial interrupts. These represent the 15 ISA

interrupts (IRQ0–1, 3–15), the four PCI interrupts, and the control signals SMI# and

IOCHK#. The serial IRQ protocol does not support the additional APIC interrupts

(20–23).

k. Section 5.13.11 Clock Generators is removed.

l. Section 5.8.4.6 Cascade Mode is removed.

m. THERM_ALERT# is changed to TEMP_ALERT# throughout document.

n. Section 10.1.36 PRSTS—Power and Reset Status Register (RCBA+3310h) bit 4 is

changed as shown:

o. The following table lists changes to terms (bit names) made throughout the

document to ensure consistent naming throughout the document.

p. The following sentence is removed from section 5.16.7:

“By using the PCH’s built-in Intel Rapid Storage Technology, there is no loss of PCI

resources (request/grant pair) or add-in card slot.”

q. Section 14.4.2.5 PxIS—Port [5:0] Interrupt Status Register (ABAR+110h, 190h,

210h, 290h, 310h, 390h) bit 23 is changed as shown:

r. Section 14.4.2.6 PxIE—Port [5:0] Interrupt Enable Register (ABAR+114h, 194h,

214h, 294h, 314h, 394h) bit 23 is changed as shown:

Bit

Description

PRSTS Field 1 — R/WC. BIOS may write to this bit field.

Old Term

New (Correct) Term

CPUSCI_STS

DMISCI_STS

CPUSMI_STS

DMISMI_STS

USB2_STS

INTEL_USB2_STS

USB2_EN

INTEL_USB2_EN

SWGPE

SWGPE_EN

SPI_SMI_STS

SPI_STS

SMI_ON_SLP_EN_STS

SLP_SMI_STS

SMI_ON_SLP_EN

SLP_SMI_EN

OS_TCO_SMI

SW_TCO_SMI

Bit

Description

Incorrect Port Multiplier Status (IPMS) — R/WC. The PCH SATA controller does not

support Port Multipliers.

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