C200 datasheet(78/82 Pages) INTEL

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Documentation Changes

Specification Update

2. The processor message interrupt delivery can be used even when the legacy

mapping is used.

3. The IA-PC HPET Specification uses the term “FSB Interrupt” to describe these type

of interrupts.

5.17.3 Periodic vs. Non-Periodic Modes

Non-Periodic Mode

Timer 0 is configurable to 32 (default) or 64-bit mode, whereas Timers 1:7 only

support 32-bit mode (See Section 20.1.5).

Warning:

Software must be careful when programming the comparator registers. If the value

written to the register is not sufficiently far in the future, then the counter may pass

the value before it reaches the register and the interrupt will be missed. The BIOS

should pass a data structure to the OS to indicate that the OS should not attempt to

program the periodic timer to a rate faster than 5 microseconds.

All of the timers support non-periodic mode.

Refer to Section 2.3.9.2.1 of the IA-PC HPET Specification for more details of this

mode.

Periodic Mode

Timer 0 is the only timer that supports periodic mode. Refer to Section 2.3.9.2.2 of the

IA-PC HPET Specification for more details of this mode.

If the software resets the main counter, the value in the comparator’s value register

needs to reset as well. This can be done by setting the TIMERn_VAL_SET_CNF bit.

Again, to avoid race conditions, this should be done with the main counter halted. The

following usage model is expected:

1. Software clears the ENABLE_CNF bit to prevent any interrupts.

2. Software Clears the main counter by writing a value of 00h to it.

3. Software sets the TIMER0_VAL_SET_CNF bit.

4. Software writes the new value in the TIMER0_COMPARATOR_VAL register.

5. Software sets the ENABLE_CNF bit to enable interrupts.

The Timer 0 Comparator Value register cannot be programmed reliably by a single

64-bit write in a 32-bit environment except if only the periodic rate is being changed

during run-time. If the actual Timer 0 Comparator Value needs to be reinitialized, then

the following software solution will always work regardless of the environment:

1. Set TIMER0_VAL_SET_CNF bit.

2. Set the lower 32 bits of the Timer0 Comparator Value register.

3. Set TIMER0_VAL_SET_CNF bit.

4. Set the upper 32 bits of the Timer0 Comparator Value register.

5.17.4 Enabling the Timers

The BIOS or operating system PnP code should route the interrupts. This includes the

Legacy Rout bit, Interrupt Rout bit (for each timer), and interrupt type (to select the

edge or level type for each timer).

C200 Datasheet(PDF) 78 Page - Intel Corporation

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