C200 datasheet(47/82 Pages) INTEL

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Specification Update

Documentation Changes

DMI L1 Exit Latency Documentation Change

Section 10.1.14 LCAP—Link Capabilities Register bits 17:15 are changed as shown:

Device 30 Function 0 Naming Consistency Change

Device 30 Function 0 is named PCI-to-PCI Bridge throughout document for consistency.

Gigabit Ethernet Capabilities and Status Registers Additions

a. The follow is added as section 12.2

12.2 Gigabit LAN Capabilities and Status Registers (CSR)

The internal CSR registers and memories are accessed as direct memory mapped

offsets from the base address register in Section 12.1.10. Software may only access

whole DWord at a time.

Note:

Reserved.

IDE_CONFIG Field 2 — R/W. This field is R/W to maintain software compatibility. This

field has no effect on hardware.

Reserved

IDE_CONFIG Field 1 — R/W. This field is R/W to maintain software compatibility. This

field has no effect on hardware.

Bit

Description

Bit

Description

17:15

L1 Exit Latency (EL1) — R/WO.

000b – Less than 1 µs

001b – 1 µs to less than 2 µs

010b – 2 µs to less than 4 µs

011b – 4 µs to less than 8 µs

100b – 8 µs to less than 16 µs

101b – 16 µs to less than 32 µs

110b – 32 µs to 64 µs

111b – More than 64 µs

Table 12-2. Gigabit LAN Capabilities and Status Registers Address Map

(Gigabit LAN —MBARA) (Sheet 1 of 2)

MBARA

+ Offset

Mnemonic

Default

Attribute

00h-03h

GBECSR1

Gigabit Ethernet Capabilities and

Status Register 1

00100241h

R/W

18h-1Bh

GBECSR2

Gigabit Ethernet Capabilities and

Status Register 2

01501000h

R/W/SN

20h-23h

GBECSR3

Gigabit Ethernet Capabilities and

Status Register 3

1000XXXXh

R/W

2Ch-2Fh

GBECSR4

Gigabit Ethernet Capabilities and

Status Register 4

00000000h

R/W

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