C200 datasheet(75/82 Pages) INTEL

75 / 82 page

Specification Update

Documentation Changes

29.

Miscellaneous Documentation Corrections VI

a. Section 15.1.33 title is changed to ATS-APM Trapping Status Register.

b. Section 16.1.37 mnemonic is changed to FLR_STAT.

30.

Miscellaneous Documentation Correction VII

Section 10.1.80 FDSW—Function Disable SUS Well Register is updated as shown:

31.

Function Level Reset Pending Status Register Correction

Section 10.1.4 FLRSTAT—Function Level Reset Pending Status Register is updated as

shown:

32.

Miscellaneous Documentation Correction VIII

In section 21.1 Serial Peripheral Interface Memory Mapped Configuration Registers, the

RCBA register cross reference is corrected to be Section 13.1.39 (the RCBA—Root

Complex Base Address Register).

INTR

Table 23-3

0200h

INTR

Section 23.2.1.12

0200h

ME_UMA

Table 23-1

80000000h

KTIIR

Section 23.4.2.6

01h

KTLCR

Section 23.4.2.8

03h

SCTLBA

Section 23.3.1.11

00000001h

Location of Incorrect

Default Value

Correct Default Value

Bit

Description

Function Disable SUS Well Lockdown (FDSWL)— R/W

0 = FDSW registers are not locked down.

1 = FDSW registers are locked down and this bit will remain set until a global reset

occurs.

NOTE: This bit must be set when Intel® Active Management Technology is enabled.

Bit

Description

31:24

Reserved

FLR Pending Status for EHCI #1 (D29) — RO.

0 = Function Level Reset is not pending.

1 = Function Level Reset is pending.

22:16

Reserved

FLR Pending Status for EHCI #2 (D26) — RO.

0 = Function Level Reset is not pending.

1 = Function Level Reset is pending.

14:0

Reserved

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