C200 datasheet(44/82 Pages) INTEL

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Documentation Changes

Specification Update

b. The following paragraph is added to the register summary of section 14.1.22

IDE_TIM — IDE Timing Register:

Bits 14:12 and 9:0 of this register are R/W to maintain software compatibility. These

bits have no effect on hardware.

c. The following registers are added immediately following section 14.1.22:

SIDETIM—Slave IDE Timing Register (SATA–D31:F2)

Address Offset: 44h

Attribute:

R/W

Default Value:

00h

Size:

8 bits

Note:

This register is R/W to maintain software compatibility. These bits have no effect on

hardware.

SDMA_CNT—Synchronous DMA Control Register

(SATA–D31:F2)

Address Offset: 48h

Attribute:

R/W

Default Value:

00h

Size:

8 bits

Note:

This register is R/W to maintain software compatibility. These bits have no effect on

hardware.

SDMA_TIM—Synchronous DMA Timing Register

(SATA–D31:F2)

Address Offset: 4Ah–4Bh

Attribute:

R/W

Default Value:

0000h

Size:

16 bits

Note:

This register is R/W to maintain software compatibility. These bits have no effect on

hardware.

14:12

IDE_TIM Field 2 — R/W. This field is R/W to maintain software compatibility. This field

has no effect on hardware.

11:10 Reserved

9:0

IDE_TIM Field 1 — R/W. This field is R/W to maintain software compatibility. This field

has no effect on hardware.

Bit

Description

Bit

Description

7:0

SIDETIM Field 1 — R/W. This field is R/W to maintain software compatibility. This field

has no effect on hardware.

Bit

Description

7:4

Reserved

3:0

SDMA_CNT Field 1 — R/W. This field is R/W to maintain software compatibility. This

field has no effect on hardware.

Bit

Description

15:14

Reserved

13:12

SDMA_TIM Field 4— R/W. This field is R/W to maintain software compatibility. This

field has no effect on hardware.

11:10

Reserved

C200 Datasheet(PDF) 44 Page - Intel Corporation

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