C200 datasheet(37/82 Pages) INTEL

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Specification Update

Specification Clarifications

NOTES:

All GPIOs can be configured as either input or output.

GPI[15:0] can be configured to cause a SMI# or SCI. Note that a GPI can be routed to either

an SMI# or an SCI, but not both.

Some GPIOs exist in the VccSus3_3 power plane. Care must be taken to make sure GPIO

signals are not driven high into powered-down planes. Also, external devices should not be

driving powered down GPIOs high. Some GPIOs may be connected to pins on devices that

exist in the core well. If these GPIOs are outputs, there is a danger that a loss of core power

(PWROK low) or a Power Button Override event will result in the PCH driving a pin to a logic

1 to another device that is powered down.

The functionality that is multiplexed with the GPIO may not be used in desktop configuration.

When this signal is configured as GPO the output stage is an open drain.

GPIO18 will toggle at a frequency of approximately 1 Hz when the signal is programmed as a

GPIO (when configured as an output) by BIOS.

For GPIOs where GPIO vs. Native Mode is configured using SPI Soft Strap, the corresponding

GPIO_USE_SEL bits for these GPIOs have no effect. The GPIO_USE_SEL bits for these GPIOs

may change to reflect the Soft-Strap configuration even though GPIO Lockdown Enable (GLE)

bit is set.

These pins are used as Functional straps. See Section 2.27 for more details.

Once Soft-strap is set to GPIO mode, this pin will default to GP Input. When Soft-strap is

SLP_LAN# usage and if Host BIOS does not configure as GP Output for SLP_LAN# control,

SLP_LAN# behavior will be based on the setting of the RTC backed SLP_LAN# Default Bit

(D31:F0:A4h:Bit 8).

10. When the multiplexed GPIO is used as GPIO functionality, care should be taken to ensure the

signal is stable in its inactive state of the native functionality, immediately after reset until it

is initialized to GPIO functionality.

11. GPIO13 is powered by VccSusHDA (either 3.3 V or 1.5 V). Voltage tolerance on the signal is

the same as VccSusHDA.

12. GPIO functionality is only available when the Suspend well is powered although pin is in

DSW.

13. GPIO will assume its native functionality until the soft strap is loaded after which time the

functionality will be determined by the soft strap setting.

b. Section 13.8.3.6 GPE0_EN—General Purpose Event 0 Enables Register bit 35 is

changed as shown:

GPIO1

I/O

3.3 V

Core

GPI

Yes

Yes2

Multiplexed with TACH1.

Mobile: Used as GPIO1 only.

GPIO0

I/O

3.3 V

Core

GPI

Yes

Yes2

Multiplexed with BMBUSY#

Table 2-24 General Purpose I/O Signals (Sheet 5 of 5)

Name

Type

Toler-

ance

Power

Well

Default

Blink

Capa-

bility

Glitch

Protection

during

Power-On

Sequence

GPI

Event

Support

Description

Bit

Description

GPIO27_EN — R/W.

0 = Disable.

1 = Enable the setting of the GPIO27_STS bit to generate a wake event/SCI/SMI#.

GPIO27 is a valid host wake event from Deep S4/S5. The wake enable configuration

persists after a G3 state.

NOTE: In the Deep S4/S5 state, GPIO27 has no GPIO functionality other than wake

enable capability, which is enabled when this bit is set.

C200 Datasheet(PDF) 37 Page - Intel Corporation

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